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參數(shù)資料
| 型號： | M41ST87YWX6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SO-28 |
| 文件頁數(shù)： | 21/38頁 |
| 文件大?。?/td> | 569K |
| 代理商： | M41ST87YWX6 |
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M41ST87Y, M41ST87W
28/38
Figure 24. Back-Up Mode Alarm Waveform
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time-
out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg-
ister = 3*1 or 3 seconds).
Note: The accuracy of the timer is within ± the se-
lected resolution.
If the processor does not reset the timer within the
specified period, the M41ST87Y/W sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the watchdog will activate the IRQ/OUT pin
when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for tREC. The Watchdog register, FT, AFE, ABE
and SQWE Bits will reset to a '0' at the end of a
Watchdog time-out when the WDS Bit is set to a
'1.'
The watchdog timer can be reset by two methods:
1) a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a WRITE of the
Watchdog Register. The time-out period then
starts over.
Note: The WDI pin should be tied to VSS if not
used.
In order to perform a software reset of the watch-
dog timer, the original time-out period can be writ-
ten
into
the
Watchdog
Register,
effectively
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, either a
transition of the WDI pin, or a value of 00h needs
to be written to the Watchdog Register in order to
clear the IRQ/OUT pin. This will also disable the
watchdog function until it is again programmed
correctly. A READ of the Flags Register will reset
the Watchdog Flag (Bit D7; Register 0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared.
AI07087
VCC
IRQ/OUT
VPFD
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
HIGH-Z
VSO
HIGH-Z
tREC
相關(guān)PDF資料 |
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|---|---|
| M41T00M6F | REAL TIME CLOCK, PDSO8 |
| M41T00M6E | REAL TIME CLOCK, PDSO8 |
| M41T00M6 | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| M41T0DS6 | REAL TIME CLOCK, PDSO8 |
| M41T0DS6T | REAL TIME CLOCK, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M41ST95WMH6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95WMH6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95WMH6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95WMH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
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