參數(shù)資料
型號(hào)： M38C59GFHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 36/71頁(yè)
文件大?。?/td> 939K
代理商： M38C59GFHP
Rev.2.00
Nov 23, 2005
page 41 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
A/D CONVERTER
The 38C5 group has a 10-bit A/D converter. The A/D converter per-
forms successive approximation conversion.The 38C5 group has the
ADKEY function which perform A/D conversion of the “L” level ana-
log input from the ADKEY pin automatically.
[AD Conversion Register (ADL, ADH)]
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored in
the AD conversion register (high-order) (address 001716), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
AD conversion register (low-order) (address 001616).
During A/D conversion, do not read these registers.
Also, the connection between the resistor ladder and reference volt-
age input pin (VREF) can be controlled by the VREF input switch bit (bit
0 of address 001616). When “1” is written to this bit, the resistor ladder
is always connected to VREF. When “0” is written to this bit, the resistor
ladder is disconnected from VREF except during the A/D conversion.
[AD Control Register (ADCON)]
This register controls A/D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 3 is an AD conversion completion bit and “0” during A/
D conversion. This bit is set to “1” upon completion of A/D conversion.
A/D conversion is started by setting “0” in this bit.
Bit 5 is the ADKEY enable bit. The ADKEY function is enabled by
setting “1” to this bit. When this function is valid, the analog input
selection bit is ignored. Also, when bit 5 is “1”, do not set “0” to bit 3
by program.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and VREF, and outputs the divided voltages.
Fig. 38 Block diagram of A/D converter
ADKEY
control circuit
AVSS
VREF
b7b0
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7/ADKEY0
Data bus
A/D interrupt request
AD control register
C
h
a
n
e
l
s
e
le
c
to
r
Comparator
A/D control circuit
AD conversion register (H) AD conversion register (L)
(Address 001716)
(Address 001616)
Resistor ladder
[Channel Selector]
The channel selector selects one of the input ports P57/AN7–P50/
AN0 and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compare an analog input voltage
with the comparison voltage and store the result in the AD conver-
sion register. When an A/D conversion is completed, the control cir-
cuit sets the AD conversion completion bit and the AD conversion
interrupt request bit to “1.”
The comparator is constructed linked to a capacitor. The conversion
accuracy may be low because the change is lost if the conversion
speed is not enough.
Accordingly, set f(XIN) to at least 500 kHz during A/D conversion in
the middle- or high- speed mode.
Also, do not execute the STP and WIT instructions during the A/D
conversion.
In the low-speed mode, since the A/D conversion is executed by the
built-in self-oscillation circuit, the minimum value of f(XIN) frequency.
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