參數(shù)資料
型號: M38C24M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 55/91頁
文件大?。?/td> 1867K
代理商: M38C24M4-XXXFP
5. Electrical Characteristics
Page 59 of 85
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85
°C unless otherwise specified)
Table 5.23
A/D Trigger Input
Table 5.24
Serial Interface
i = 0 to 6
Table 5.25
Intelligent I/O Communication Function (Groups 0 and 1)
i = 0, 1
Table 5.26
Intelligent I/O Communication Function (Group 2)
Symbol
Parameter
Standard
Unit
Min.
Max.
tc(AD)
ADTRG input cycle time (required for trigger)
1000
ns
tw(ADL)
ADTRG input low (“L”) pulse width
125
ns
Symbol
Parameter
Standard
Unit
Min.
Max.
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high (“H”) pulse width
100
ns
tw(CKL)
CLKi input low (“L”) pulse width
100
ns
td(C-Q)
TXDi output delay time
80
ns
th(C-Q)
TXDi output hold time
0
ns
tsu(D-C)
RXDi input setup time
70
ns
th(C-D)
RXDi input hold time
90
ns
Symbol
Parameter
Standard
Unit
Min.
Max.
tc(CK)
ISCLKi input cycle time
600
ns
tw(CKH)
ISCLKi input high (“H”) pulse width
300
ns
tw(CKL)
ISCLKi input low (“L”) pulse width
300
ns
td(C-Q)
ISTXDi output delay time
100
ns
th(C-Q)
ISTXDi output hold time
0
ns
tsu(D-C)
ISRXDi input setup time
100
ns
th(C-D)
ISRXDi input hold time
100
ns
Symbol
Parameter
Standard
Unit
Min.
Max.
tc(CK)
ISCLK2 input cycle time
600
ns
tw(CKH)
ISCLK2 input high (“H”) pulse width
300
ns
tw(CKL)
ISCLK2 input low (“L”) pulse width
300
ns
td(C-Q)
ISTXD2 output delay time
180
ns
th(C-Q)
ISTXD2 output hold time
0
ns
tsu(D-C)
ISRXD2 input setup time
150
ns
th(C-D)
ISRXD2 input hold time
100
ns
VCC1 = VCC2 = 5V
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