- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45046 > M38507M8A-XXXSP 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDIP42 PDF資料下載
參數(shù)資料
| 型號： | M38507M8A-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 13 X 36.72 MM, 1.78 MM PITCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 82/90頁 |
| 文件大小： | 899K |
| 代理商： | M38507M8A-XXXSP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁當前第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
3850 Group (Spec.A)
Rev.2.10
2005.11.14
page 81 of 86
REJ03B0093-0210
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
APPENDIX
NOTES ON PROGRAMMING
1. Processor status register
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because
they have an important effect on calculations.
<Reason>
After a reset, the contents of the processor status register (PS)
are undefined except for the I flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 2 Stack memory contents after PHP instruction execution
Fig. 1 Initialization of processor status register
(2) How to reference the processor status register
To reference the contents of the processor status register (PS), ex-
ecute the PHP instruction once then read the contents of (S+1). If
necessary, execute the PLP instruction to return the PS to its origi-
nal status.
(S)
(S)+1
Stored PS
4. JMP instruction
When using the JMP instruction in indirect addressing mode, do
not specify the last address on a page as an indirect address.
5. Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
The execution of these instructions does not change the con-
tents of the processor status register.
6. Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is “1”
The addressing mode which uses the value of a direction regis-
ter as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
7. Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock
φ by the number of cycles men-
tioned in the 740 Family Software Manual.
The frequency of the internal clock
φ is the twice the XIN cycle in
high-speed mode, 8 times the XIN cycle in middle-speed mode,
and the twice the XCIN in low-speed mode.
Set D flag to “1”
↓
ADC or SBC instruction
↓
↓
SEC, CLC, or CLD instruction
Fig. 3 Execution of decimal calculations
3. Decimal calculations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper
decimal notation, set the decimal mode flag (D) to “1” with the
SED instruction. After executing the ADC or SBC instruction, ex-
ecute another instruction before executing the SEC, CLC, or CLD
instruction.
(2) Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC or
SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of
the calculation, or is cleared to “0” if a borrow is generated. To de-
termine whether a calculation has generated a carry, the C flag
must be initialized to “0” before each calculation. To check for a
borrow, the C flag must be initialized to “1” before each calcula-
tion.
2. BRK instruction
(1) Interrupt priority level
When the BRK instruction is executed with the following condi-
tions satisfied, the interrupt execution is started from the address
of interrupt vector which has the highest priority.
Interrupt request bit and interrupt enable bit are set to “1”.
Interrupt disable flag (I) is set to “1” to disable interrupt.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M38504M6A-XXXFP | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42 |
| M38503M4A-XXXSP | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDIP42 |
| M38503M4A-XXXFP | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42 |
| M38504M6A-XXXSP | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDIP42 |
| M38513M4-XXXFP | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3851 BK001 | 制造商:Alpha Wire Company 功能描述:CBL 7COND 14AWG BLK 1000' |
| M3851 BK002 | 制造商:Alpha Wire Company 功能描述:CBL 7COND 14AWG BLK 500' |
| M3851 BK005 | 制造商:Alpha Wire Company 功能描述:CBL 7COND 14AWG BLK 100' |
| M38510/00102BCB | 制造商:n/a 功能描述:38510/00102 S6I6B 制造商: 功能描述: 制造商:undefined 功能描述: |
| M38510/00103BCA | 制造商:QP Semiconductor 功能描述:NAND GATE, TRIPLE 3-INPUT |
發(fā)布緊急采購，3分鐘左右您將得到回復。