
HARDWARE
3850 Group (Spec. H) User’s Manual
FUNCTIONAL DESCRIPTION
1-14
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Pin
Name
Input/Output
I/O Structure
Non-Port Function
Table 7 I/O port function
Related SFRs
Port P0
Port P1
Port P2
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
P10–P17
P20/XCOUT
P21/XCIN
P22
P23
P24/RxD
P25/TxD
P26/SCLK1
P27/CNTR0/SRDY1
P30/AN0–
P34/AN4
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
CMOS compatible
input level
CMOS 3-state output
Serial I/O2 function I/O
Serial I/O2 control register
Sub-clock generating
circuit
CPU mode register
CMOS compatible
input level
CMOS 3-state output
Input/output,
individual
bits
Interrupt edge selection
register
PWM control register
External interrupt input
PWM output
Ref.No.
(5)
(1)
(2)
(3)
(4)
(6)
(7)
(8)
(9)
(10)
(11)
(17)
CMOS compatible
input level
N-channel open-drain
output
Serial I/O1 control register
Serial I/O1 function I/O
Timer X function I/O
Serial I/O1 control register
Timer XY mode register
(12)
Timer Y function I/O
A-D conversion input
A-D control register
Timer XY mode register
(13)
(14)
(15)
(16)
Interrupt edge selection
register
External interrupt input
SCMP2 output
Interrupt edge selection
register
Serial I/O2 control register
P44/INT3/PWM
Port P3
Port P4
Note: When bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined.