參數(shù)資料
型號(hào)： M38504M6A-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42
封裝： 8.40 X 17.50 MM, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數(shù)： 27/59頁
文件大?。?/td> 885K
代理商： M38504M6A-XXXFP
Rev.2.13
Apr 17, 2009
Page 33 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
A/D CONVERTER
[AD Conversion Registers (ADL, ADH)] 003516, 003616
The AD conversion registers are read-only registers that store the
result of an A/D conversion. Do not read these registers during
an A/D conversion.
[AD Control Register (ADCON)] 003416
The AD control register controls the A/D conversion process.
Bits 0 to 2 select a specific analog input pin. By setting a value to
these bits, when bit 0 of the AD input selection register (address
003716) is “0”, P30/AN0-P34/AN4 can be selected, and when bit
0 of the AD input selection register is “1”, P04/AN5-P07/AN8 can
be selected.
Bit 4 indicates the completion of an A/D conversion. The value
of this bit remains at “0” during an A/D conversion and changes
to “1” when an A/D conversion ends. Writing “0” to this bit starts
the A/D conversion.
[AD Input Selection Register (ADSEL)] 003716
The analog input port selection switch bit is assigned to bit 0 of
the AD input selection register. When “0” is set to the analog
input port selection switch bit, P30/AN0-P34/AN4 can be selected
by the analog input pin selection bits (b2, b1, b0) of the AD
control register (address 003416). When “1” is set to the analog
input port selection switch bit, P04/AN5-P07/AN8 can be selected
by the analog input pin selection bits (b2, b1, b0) of the AD
control register (address 003416).
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024 and outputs the divided voltages.
Channel Selector
The channel selector selects one of ports P30/AN0 to P34/AN4,
P04/AN5 to P07/AN8 and inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compare an analog input
voltage with the comparison voltage, and the result is stored in
the AD conversion registers. When an A/D conversion is
completed, the control circuit sets the AD conversion completion
bit and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor
coupling, set f(XIN) to 500 kHz or more during an A/D
conversion.
When the A/D converter is operated at low-speed mode, f(XIN)
and f(XCIN) do not have the lower limit of frequency, because of
the A/D converter has a built-in self-oscillation circuit.
Fig 33. Structure of AD control register
Fig 34. Structure of AD input selection register
Fig 35. Structure of AD conversion registers
AD control register
(ADCON : address 003416)
Analog input pin selection bits
0 0 0: P30/AN0or P04/AN5
0 0 1: P31/AN1or P05/AN6
0 1 0: P32/AN2or P06/AN7
0 1 1: P33/AN3or P07/AN8
1 0 0: P34/AN4
Not used (returns “0” when read)
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
b7
b0
b2 b1 b0
Note 1
Note 2
Notes 1: This is selected when bit 0 of the AD input selection register
(address 003716) is “0”.
2: This is selected when bit 0 of the AD input selection register
(address 003716) is “1”.
AD input selection register
(ADSEL: address 003716)
Analog input port selection switch bit
0: P30/AN0 to P34/AN4 is selected as
analog input pin.
1: P04/AN5 to P07/AN8 is selected as
analog input pin.
Not used (returns “0” when read)
Fix this bit to “0”.
Not used (returns “0” when read)
Fix this bit to “0”.
b7
b0
8-bit reading (Read only address 003516)
(Address 003516)
10-bit reading
(Read address 003616 before 003516)
(Address 003616)
(Address 003516)
Note : The high-order 6 bits of address 003616 become “0”
at reading.
b7
b0
b9 b8
b7
b0
b6 b5 b4 b3 b2 b1 b0
b9
b7
b0
b8 b7 b6 b5 b4 b3 b2
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