參數(shù)資料
型號: M3823AGFHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 42/76頁
文件大?。?/td> 896K
代理商: M3823AGFHP
Rev.2.02
Jun 19, 2007
page 47 of 73
REJ03B0146-0202
3823 Group
φ
φφ
φ
φ CLOCK SYSTEM OUTPUT FUNCTION
The internal system clock φ or XCIN frequency signal can be out-
put from port P41 by setting the φ output control register. Set bit 1
of the port P4 direction register to “1” when outputting φ clock.
Fig. 45 Structure of φ
φφ
φ
φ output control register
φ output control register
(CKOUT : address 002A16)
φ output control bit
0 : port function
1 : φ clock output or XCIN frequency signal output
Not used (return “0” when read)
b7
b0
Temporary data register
The temporary data register (addresses 002C16 to 002E16) is the
8-bit register and does not have the control function. It can be
used to store data temporarily. It is initialized after reset.
RRF register
The RRF register (address 002F16)is the 8-bit register and does
not have the control function. As for the value written in this regis-
ter, high-order 4 bits and low-order 4 bits interchange. It is
initialized after reset.
Fig. 46 Structure of temporary register, RPF register
Set the bit 4 in the peripheral function expansion register to “1”
when the XCIN frequency signal is output.
b7
b0
Temporary data register 0,1,2
(Address: 002C16, 002D16, 002E16)
DB0 data storage
DB1 data storage
DB2 data storage
DB3 data storage
DB4 data storage
DB5 data storage
DB6 data storage
DB7 data storage
TD0,TD1,TD2
b7b0
RRF register (Address: 002F16)
DB4 data storage
DB5 data storage
DB6 data storage
DB7 data storage
DB0 data storage
DB1 data storage
DB2 data storage
DB3 data storage
RRFR
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