參數(shù)資料
型號: M3823AGFHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 38/76頁
文件大?。?/td> 896K
代理商: M3823AGFHP
Rev.2.02
Jun 19, 2007
page 43 of 73
REJ03B0146-0202
3823 Group
LCD Display RAM
Address 004016 to 004F16 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
Fig. 39 LCD display RAM map
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the
following equation;
f(LCDCK) =
Frame frequency =
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)
(duty ratio)
Bit
Address
7
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
COM3
0
1
2
3
4
5
6
COM0
COM1
COM2
COM3
COM0
COM1
COM2
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
STP Instruction Execution
Execution of the STP instruction sets the LCD enable bit (bit 3 of
the LCD mode register) to “0” and the LCD panel turns off.To
make the LCD panel turn on after returning from the stop mode,
set the LCD enable bit to “1”.
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