參數(shù)資料
型號: M3823AGF-XXXHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 44/76頁
文件大小: 896K
代理商: M3823AGF-XXXHP
Rev.2.02
Jun 19, 2007
page 49 of 73
REJ03B0146-0202
3823 Group
PERIPHERAL FUNCTION EXTENSION REGISTER
The serial I/O transfer direction can be switched by setting the bit
0 in the peripheral function expansion register to “1”. This function
is valid only when the bit 6 in the serial I/O control register is set to
“1” (when the clock synchronous serial I/O is selected). P47 can
be selected as the output pin of the clock synchronous serial I/O
by setting the bit 1 in the peripheral function expansion register to
“1”. When setting P47 to the SOUT pin, set the bit 7 in the port P4
direction register to “1”. This function is valid only when the bit 6 in
the serial I/O control register to “1” (when the clock synchronous
serial I/O is selected). P-channel output of TXD and SOUT can be
disabled by the bits 2 and 3 in the peripheral function expansion
register. Set the bit 4 in the UART control register to “1” after se-
lecting the pin to disable the P-channel output. XCIN frequency
signal can be output from the port P41 by setting the bit 4 in the
peripheral function expansion register to “1”. Set the bit 0 in the φ
output control register and the bit 1 in the port P4 direction regis-
ter to “1” to output the XCIN frequency signal.
Fig. 50 Structure of peripheral function extension register
Transfer direction selection bit (valid when UART is used)
0 : LSB first
1 : MSB first
Synchronous serial I/O output pin selection bit
0:P45/TXD pin
1:P47/SRDY/SOUT pin
P-channel output disabled selection bit
00: P45/TXD pin
01: The bit 4 in the UART control register is invalid
10: P45/TXD pin or P47/SRDY/SOUT pin
11: P47/SRDY/SOUT pin
Output clock selection bit
0: φ clock output
1: XCIN frequency signal output
Not used (returns “0” when read)
(Do not write “1” to this bit)
Peripheral function extension register (Address: 003016)
EXP
b7b0
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