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參數(shù)資料
| 型號： | M3823AGF-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 27/76頁 |
| 文件大?。?/td> | 896K |
| 代理商： | M3823AGF-XXXHP |
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Rev.2.02
Jun 19, 2007
page 33 of 73
REJ03B0146-0202
3823 Group
SERIAL INTERFACE
Serial I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O can be selected by setting the mode
selection bit of the serial I/O control register to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
The MSB first transfer is selected as the transfer direction by setting
the bit 0 in the peripheral function expansion register to “1”. Also, the
synchronous serial I/O output switches to the P47/SRDY/SOUT pin by
setting the bit 1 in the peripheral function expansion register to “1”.
Fig. 26 Block diagram of clock synchronous serial I/O
Fig. 27 Operation of clock synchronous serial I/O function
P46/SCLK
P47/SRDY1/SOUT
P44/RXD
P45/TXD
f(XIN)
1/4
F/F
Serial I/O status register
Serial I/O control register
Receive buffer register
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Data bus
Address 001816
Shift clock
Transmit shift register shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Data bus
Address 001A16
Transmit buffer register
Transmit shift register
(f(SUB) in low-speed mode)
Transfer direction selection bit
Serial output pin selection bit
Serial output pin
selection bit
Transfer direction
selection bit
Note: f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Receive enable signal SRDY
D7
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
(or SOUT)
Serial input RXD
Write signal to receive/transmit
buffer register (address 001816)
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
D7
D0
D1
D2
D3
D4
D5
D6
TxD and RxD above shows the operation when selecting LSB first transfer.
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