![](http://datasheet.mmic.net.cn/30000/M38223E4-XXXHP_datasheet_2360327/M38223E4-XXXHP_327.png)
P2-71
(2) Timer Y
s Period measurement
mode
Fig. 2.3.28
P2-72
(2) Timer Y
s Event counter mode
Fig. 2.3.29
P2-73
(2) Timer Y
s Pulse width HL con-
tinuously measure-
ment mode
Fig. 2.3.30
Previous change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before setting below, clear the interrupt enable bits (timer
Y or CNTR1) and the interrupt request bits (timer Y or CNTR1)
to “0”.
After setting below, set the interrupt enable bits (timer Y
or CNTR1) to “1” (interrupts enabled).
After change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before timer Y stops counting (before setting below), clear
the interrupt enable bit (timer Y or CNTR1) to “0”.
After setting below, clear the interrupt request bit (timer Y
or CNTR1) to “0” and next set the interrupt enable bit (timer
Y or CNTR1) to “1” (interrupt enabled).
Set last.
Previous change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before setting below, clear the interrupt enable bits (timer
Y or CNTR1) and the interrupt request bits (timer Y or CNTR1)
to “0”.
After setting below, set the interrupt enable bits (timer Y
or CNTR1) to “1” (interrupts enabled).
After change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before timer Y stops counting (before setting below), clear
the interrupt enable bit (timer Y or CNTR1) to “0”.
After setting below, clear the interrupt request bit (timer Y
or CNTR1) to “0” and next set the interrupt enable bit (timer
Y or CNTR1) to “1” (interrupt enabled).
Set last.
Previous change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before setting below, clear the interrupt enable bits (timer
Y or CNTR1) and the interrupt request bits (timer Y or CNTR1)
to “0”.
After setting below, set the interrupt enable bits (timer Y
or CNTR1) to “1” (interrupts enabled).
After change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before timer Y stops counting (before setting below), clear
the interrupt enable bit (timer Y or CNTR1) to “0”.
After setting below, clear the interrupt request bit (timer Y
or CNTR1) to “0” and next set the interrupt enable bit (timer
Y or CNTR1) to “1” (interrupt enabled).
Set last.
Corrections and Supplementary Explanation for “3822 Group User’s Manuals” No.3
M380-17-9910
(4/5)
Page
Rev.
Contents
B