2.3 Timer X and timer Y
APPLICATION
2–61
3820 GROUP USER’S MANUAL
Table 2.3.3 Relation between timer Y operating mode bits
and operating modes
b5 b4
0 0
0 1
1 0
1 1
Operation mode
Timer mode
Period measurement mode
Event counter mode
Pulse width HL continuously measurement mode
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Timer Y operating mode bits (bit 4 and bit 5)
The timer Y operating mode bits select a op-
erating mode of the timer Y.
Table 2.3.3 shows the relation between the timer
Y operating mode bits and the operating modes.
For an explanation of each mode operation,
refer to the section pertaining to the explana-
tion of each operation.
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CNTR
1
active edge switch bit (bit 6)
The CNTR
1
active edge switch bit has a function which selects an active edge of the CNTR
1
interrupt
and functions for each mode.
In the pulse width HL continuously measurement mode, this bit is invalid.
G
CNTR
1
interrupt
When bit 6 is “0,” the falling edge ( ) is active.
When bit 6 is “1,” the rising edge ( ) is active.
In the pulse width HL continuously measurement mode, an interrupt request occurs at the both
edges regardless of the value of this bit.
G
Period measurement mode
This bit selects the duration which is measured.
When bit 6 is “0,” the falling edge to the falling edge duration is measured.
When bit 6 is “1,” the rising edge to the rising edge duration is measured.
G
Event counter mode
An active edge of the count source is selected.
When bit 6 is “0,” the rising edge ( ) is active.
When bit 6 is “1,” the falling edge ( ) is active.
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Timer Y stop control bit (bit 7)
The timer Y stop control bit controls the count operation of the timer Y.
By writing “0” to bit 7, a count source is input to the Y counter, so that a count operation is started.
As bit 7 is in the “0” state immediately after reset release, the count operation is automatically started
after reset release.
By writing “1” to bit 7, the input of count source to the Y counter is stopped, so that the count operation
stops.
At read, this bit functions as a status bit to indicate the operating state (counting or stop) of the
counter. When bit 7 is “0,” the counter is in the operating state. When bit 7 is “1,” the counter is in
the stop state.