APPLICATION
2.9 Standby function
3820 GROUP USER’S MANUAL
2–184
2.9.3 State transitions of internal clock
φ
Figure 2.9.4 shows the state transitions of the internal clock
φ
when the standby function is used.
Fig. 2.9.4 State transitions of internal clock
φ
RESET
CM
6
“1”
“0”
CM
5
“1
“0
CM
6
“1
“0
CM
5
“0
“1
CM
6
“1
“0
CM
4
“1
“0
CM
6
“1
“0
CM
4
“0
“1
CM
6
“1
“0
CPU mode register (CPUM)
[Address 3B
16
]
CM
4
: Port Xc switch bit
0: I/O port
1: X
CIN
, X
COUT
CM
5
: Main clock (X
IN
–X
OUT
) stop bit
0: Oscillating
1: Stopped
CM
6
: Main clock division ratio selection bit
0: f(X
IN
)/2 (high-speed mode)
1: f(X
IN
)/8 (middle-speed mode)
CM
7
: Internal system clock selection bit
0: X
IN
–X
OUT
selected
(middle-/high-speed mode)
1: X
–X
selected
(low-speed mode)
Middle-speed mode
(f (
φ
) = 1 MHz)
CM
7
= 0 (8 MHz selected)
CM
6
= 1 (Middle-speed)
CM
5
= 0
(8 MHz oscillating)
CM
4
= 0
(32 kHz stopped)
High-speed mode
(f (
φ
) = 4 MHz)
CM
7
= 0 (8 MHz selected)
CM
6
= 0 (High-speed)
CM
5
= 0
(8 MHz oscillating)
CM
4
= 0
(32 kHz stopped)
C
4
“
“
C
4
“
“
Middle-speed mode
(f (
φ
) = 1 MHz)
CM
7
= 0 (8 MHz selected)
CM
6
= 1 (Middle-speed)
CM
5
= 0
(8 MHz oscillating)
CM
4
= 1
(32 kHz oscillating
)
High-speed mode
(f (
φ
) = 4 MHz)
CM
7
= 0 (8 MHz selected)
CM
6
= 0 (High-speed)
CM
5
= 0
(8 MHz oscillating)
CM
4
= 1
(32 kHz oscillating
)
CM6
“1”
“0”
C
7
“
“
Low-speed mode
(f (
φ
) = 16 kHz)
CM
7
= 1
(32 kHz selected)
CM
6
= 1 (Middle-speed)
CM
5
= 0
(8 MHz oscillating)
CM
4
= 1 (32
kHz oscillating
)
CM
6
“1”
“0”
C
7
“
“
Low-speed mode
(f (
φ
) = 16 kHz)
CM
7
= 1
(32 kHz selected)
CM
6
= 0 (High-speed)
CM
5
= 0
(8 MHz oscillating)
CM
4
= 1 (32
kHz oscillating
)
C
5
“
“
C
5
“
“
CM
6
“1”
“0”
Low-speed mode
(f (
φ
) = 16 kHz)
CM
7
= 1
(32 kHz selected)
CM
6
= 1 (Middle-speed)
CM
5
= 1 (8 MHz stopped)
CM
4
= 1 (32
kHz oscillating
)
Low-speed mode
(f (
φ
) = 16 kHz)
CM
7
= 1
(32 kHz selected)
CM
6
= 0 (High-speed)
CM
5
= 1 (8 MHz stopped)
CM
4
= 1 (32
kHz oscillating
)
b4
b7
Notes 1:
Switch the mode by the allows shown between the mode blocks.( Do not switch between the mode
directly without an allow.)
2:
The all modes can be switched to the stop mode or the wait mode and returned to the source mode when
the stop mode or the wait mode is released.
3:
Timer and LCD operate in the wait mode.
4:
In middle-/high-speed mode, when the stop mode is released, a delay of approximately 1 ms occurs
automatically by timer 1 and timer 2.
5:
In low-speed mode, when the stop mode is released, a delay of approximately 0.25 s occurs automatically
by timer 1 and timer 2.
6:
Wait until oscillation stabilizes after oscillating the main clock X
IN
before the switching from the low-speed
mode to the middle-/high-speed mode.
7:
The example assumes that 8 MHz is being applied to the X
IN
pin and 32 kHz to the X
CIN
pin.
φ
indicates
the internal clock.