2.3 Timer X and timer Y
APPLICATION
2–83
3820 GROUP USER’S MANUAL
I
Real time port function
G
After reset release, the port P6 direction register is set for the input mode, so the pins P6
0
and P6
1
function as ordinary I/O ports. For the pin to be used as RTP, be sure to set the corresponding bits
of the port P6 direction register for the output mode.
G
For a pin used as RTP, do not change this port for the input mode during real time port operation.
G
Change RTP output data as required, for example, by using a timer X interrupt.
(2) Timer Y
I
Common to all modes
G
When reading or writing for timer Y, be sure to execute for both the timer Y (high-order) and the
timer Y (low-order). When reading a value from the timer Y, read it in the order of the timer Y (high-
order) and the timer Y (low-order). When writing a value to the timer Y, execute in the order of the
timer Y (low-order) and the timer Y (high-order). If the following operations are performed for the
timer Y, abnormal operation will occur.
Write operation before execution of timer Y (low-order) reading
Read operation before execution of timer Y (high-order) writing
I
Period measurement mode
G
In the period measurement mode, set the bit 5 (corresponding to the P5
5
/CNTR
1
) of the port P5
direction register (address 000B
16
) to “0” (input mode).
G
Setting the CNTR
1
active edge switch bit effects on the active edge of an interrupt. Consequently,
the CNTR
1
interrupt request may be caused by setting the CNTR
1
active edge switch bit.
As a countermeasure, switch the active edge after disabling the CNTR
1
interrupt, then set the
CNTR
1
interrupt request bit to “0.”
G
The maximum input frequency in the period measurement mode is:
4 MHz (250 ns) ..................................................at V
CC
= 4.0 V to 5.5 V
V
CC
– 2
(2
V
CC
) – 4 MHz ( 500
CC
= 2.5 V to 4.0 V
The minimum “H” pulse width is:
105 ns ..................................................................at V
CC
= 4.0 V to 5.5 V
V
CC
– 2
( 250
CC
= 2.5 V to 4.0 V
The minimum “L” pulse is:
105 ns ..................................................................at V
CC
= 4.0 V to 5.5 V
V
CC
– 2
( 250
CC
= 2.5 V to 4.0 V
I
Event counter mode
G
In the event counter mode, set the bit 5 (corresponding to the P5
5
/CNTR
1
) of the port P5 direction
register (address 000B
16
) to “0” (input mode).
G
Setting the CNTR
1
active edge switch bit, the active edge of an interrupt is also affected. Conse-
quently, a CNTR
1
interrupt request may be caused by setting the CNTR
1
active edge switch bit.
G
The maximum input frequency in the event counter mode is:
4 MHz (250 ns) ..................................................at V
CC
= 4.0 V to 5.5 V
V
CC
– 2
(2
V
CC
) – 4 MHz ( 500
CC
= 2.5 V to 4.0 V
The minimum “H” pulse width is:
105 ns ..................................................................at V
CC
= 4.0 V to 5.5 V
250
V
CC
– 2
( – 20 ns)...........................................at V
CC
= 2.5 V to 4.0 V