APPLICATION
2.9 Standby function
3820 GROUP USER’S MANUAL
2–180
(3) Notes on using the stop mode
I
Release sources
The release sources of the stop mode are shown below.
Reset input
INT
0
–INT
3
interrupts
Serial I/O1 transmit/receive and serial I/O2 interrupts using an external clock
Timers X/Y interrupts using an external clock
Key input interrupt (key-on wake up)
Each INT pin (INT
0
, INT
1
, INT
2
, INT
3
) is also used as ports P4
2
, P4
3
, P5
7
or P6
0
and each key input
pin is also used as port P2. To use INT
0
to INT
3
interrupts, after setting the corresponding bits of the
following direction registers to “0” to set them for the input mode, execute the
STP
instruction.
Port P2 direction register (address 0005
16
)
Port P4 direction register (address 0009
16
)
Port P5 direction register (address 000B
16
)
Port P6 direction register (address 000D
16
)
I
Register setting
To use the above interrupt requests for restoration from the stop mode, after setting the following,
execute the
STP
instruction in order to enable the interrupt request to be used.
[Necessary register setting]
Interrupt disable flag I = “0” (interrupts enabled)
Both timers 1 and 2 interrupt enable bits = “0” (interrupts disabled)
Interrupt request bit of the interrupt source to be used for restoration = “0” (no interrupt request
issued)
Interrupt enable bit of the interrupt source to be used for restoration = “1” (interrupts enabled)
At restoration from the stop mode, the values of the timers 1, 2 and 123 mode registers are auto-
matically rewritten. Accordingly, set each of them again.
To prevent a DC voltage from being applied to the LCD, after setting the LCD enable bit (bit 3) of
the LCD mode register to “0,” execute the
STP
instruction.
Write to the watchdog timer control register (address 0037
16
) before the
STP
instruction execution.
If the
STP
instruction is executed without writing, an internal reset may occures.
I
Clock after restoration
After restoration from the stop mode by an interrupt request, the contents of the CPU mode register
previous to the
STP
instruction execution are held. Accordingly, when both X
IN
and X
CIN
were oscil-
lating before execution of the
STP
instruction, the oscillation of both X
IN
and X
CIN
is resumed at
restoration from the stop mode by an interrupt request.
In the above case, when the X
IN
side is set as a system clock, the oscillation stabilizing time for
approximately 8,000 cycles of the X
IN
input is reserved at restoration from the stop mode.
At this time, note that the oscillation on the X
CIN
side may not be stabilized even after the lapse of
the oscillation stabilizing time (of the X
IN
side).