參數(shù)資料
型號(hào)： M381L6523DUM-CB3
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
中文描述： DDR SDRAM的緩沖模塊184pin緩沖模塊的發(fā)展為本的512Mb芯片與64/72-bit非ECC /有鉛ECC的66 TSOP-II免費(fèi)（符合RoHS）
文件頁(yè)數(shù)： 16/25頁(yè)
文件大?。?/td> 463K
代理商： M381L6523DUM-CB3
DDR SDRAM
256MB, 512MB, 1GB Unbuffered DIMM
Rev. 0.1 June 2005
Parameter
Symbol
CC
(DDR400@CL=3.0)
Min
55
70
40
15
15
10
15
2
-
6
5
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.7
0.7
-0.65
-0.65
10
0.4
B3
(DDR333@CL=2.5)
Min
60
72
42
18
18
12
15
1
7.5
6
-
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
0.8
-0.7
-0.7
12
0.45
Unit
Note
Max
Max
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
70K
70K
Clock cycle time
CL=2.0
CL=2.5
CL=3.0
tCK
-
12
12
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.6
1.25
12
10
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS
tCH
tCL
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tIS
tIH
tHZ
tLZ
tMRD
tDS
22
13
15, 17~19
15, 17~19
16~19
16~19
11
11
+0.65
+0.65
+0.7
+0.7
j, k
DQ & DM hold time to DQS
tDH
0.4
0.45
j, k
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
tIPW
tDIPW
tXSNR
tXSRD
tREFI
2.2
1.75
75
200
2.2
1.75
75
200
ns
ns
ns
tCK
us
18
18
7.8
7.8
14
Output DQS valid window
tQH
tHP
-tQHS
tCLmin
or tCHmin
-
tHP
-tQHS
tCLmin
or tCHmin
-
ns
21
Clock half period
tHP
-
-
ns
20, 21
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
tQHS
tWPST
0.5
0.6
0.55
0.6
ns
tCK
21
12
0.4
0.4
tRAP
15
18
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
23
12.0 AC Timming Parameters & Specifications
相關(guān)PDF資料
PDF描述
M381L2923CUM-CCC DDR SDRAM Unbuffered Module
M381L6523CUM-CLCC DDR SDRAM Unbuffered Module
M381L2923DUM-LB3 DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
M381L6523DUM-LCC DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
M381L2923DUM-LCC DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
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