參數(shù)資料
型號(hào)： M381L6523DUM-CB3
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
中文描述： DDR SDRAM的緩沖模塊184pin緩沖模塊的發(fā)展為本的512Mb芯片與64/72-bit非ECC /有鉛ECC的66 TSOP-II免費(fèi)（符合RoHS）
文件頁(yè)數(shù)： 15/25頁(yè)
文件大?。?/td> 463K
代理商： M381L6523DUM-CB3
DDR SDRAM
256MB, 512MB, 1GB Unbuffered DIMM
Rev. 0.1 June 2005
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
°
C, f=1MHz)
11.0 Input/Output Capacitance
Parameter
Symbol
M368L3324DUS
Min
41
34
34
25
6
6
-
M368L6523DUS
Min
49
42
42
25
6
6
-
M381L6523DUM
Min
51
44
44
25
6
6
6
Unit
Max
45
38
38
30
7
7
-
Max
57
50
50
30
7
7
-
Max
60
53
53
30
7
7
7
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0)
Input capacitance( CS0)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
Parameter
Symbol
M368L2923DUN
Min
65
42
42
28
10
10
-
M381L2923DUM
Min
69
44
44
28
10
10
10
Unit
Max
81
50
50
34
12
12
-
Max
87
53
53
34
12
12
12
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
Max
Unit
V
V
V
V
Note
3
3
1
2
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VREF + 0.31
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
0.7
0.5*VDDQ-0.2
10.0 AC Operating Conditions
相關(guān)PDF資料
PDF描述
M381L2923CUM-CCC DDR SDRAM Unbuffered Module
M381L6523CUM-CLCC DDR SDRAM Unbuffered Module
M381L2923DUM-LB3 DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
M381L6523DUM-LCC DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
M381L2923DUM-LCC DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
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