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| 型號(hào)： | M3819 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 8-Bit Single Chip Microcomputer(8位單片微控制器) |
| 中文描述： | 8位單片機(jī)（8位單片微控制器） |
| 文件頁(yè)數(shù)： | 12/217頁(yè) |
| 文件大?。?/td> | 2564K |
| 代理商： | M3819 |
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3819 Group USER’S MANUAL
Table of contents
viii
Fig. 2.9.8 Structure of Interrupt control register 1 ......................................................................... 158
Fig. 2.9.9 Structure of Interrupt control register 2 ......................................................................... 159
Fig. 2.9.10 Connection diagram [Status transition upon a power failure]................................... 160
Fig. 2.9.11 Status transition diagram upon a power failure.......................................................... 160
Fig. 2.9.12 Setting of related registers [Status transition upon a power failure] ....................... 161
Fig. 2.9.13 Control procedure [Status transition upon a power failure] ...................................... 162
Fig. 2.9.14 Connection diagram [Counting without clock errors during a power failure].......... 163
Fig. 2.9.15 Timing chart of counting without clock errors during a power failure ..................... 163
Fig. 2.9.16 Structure of a clock counter .......................................................................................... 164
Fig. 2.9.17 Setting of related registers (1)
[Counting without clock errors during a power failure] ...........
165
Fig. 2.9.18 Setting of related registers (2)
[Counting without clock errors during a power failure] ...........
166
Fig. 2.9.19 Control procedure (1) [Counting without clock errors during a power failure]....... 167
Fig. 2.9.20 Control procedure (2) [Counting without clock errors during a power failure]....... 168
Fig. 3.1.1 Structure of interrupt control register 2.......................................................................... 170
Fig. 3.2.1 Wiring for the RESET pin ................................................................................................ 174
Fig. 3.2.2 Wiring for clock I/O pins .................................................................................................. 175
Fig. 3.2.3 Wiring for the V
PP
pin of the One Time PROM and the EPROM version ............... 175
Fig. 3.2.4 Bypass capacitor across the V
SS
line and the V
CC
line ............................................. 175
Fig. 3.2.5 Analog signal line and a resistor and a capacitor ....................................................... 176
Fig. 3.2.6 Wiring for a large current signal line ............................................................................. 176
Fig. 3.2.7 Wiring to a signal line where potential levels change frequently .............................. 176
Fig. 3.2.8 Setup for I/O ports ............................................................................................................ 177
Fig. 3.2.9 Watchdog timer by software ............................................................................................ 177
Fig. 3.3.1 Structure of Port Pi direction register ............................................................................ 179
Fig. 3.3.2 Structure of Port P2 direction register ........................................................................... 179
Fig. 3.3.3 Structure of Serial I/O automatic transfer data pointer ............................................... 180
Fig. 3.3.4 Structure of Serial I/O 1 control register ....................................................................... 180
Fig. 3.3.5 Structure of Serial I/O automatic transfer control register .......................................... 181
Fig. 3.3.6 Structure of Serial I/O automatic transfer interval register ......................................... 181
Fig. 3.3.7 Structure of Serial I/O 2 control register ....................................................................... 182
Fig. 3.3.8 Structure of Serial I/O 3 control register ....................................................................... 182
Fig. 3.3.9 Structure of Timer 12 mode register .............................................................................. 183
Fig. 3.3.10 Structure of Timer 34 mode register ............................................................................ 183
Fig. 3.3.11 Structure of Timer 56 mode register ............................................................................ 184
Fig. 3.3.12 Structure of AD/DA control register.............................................................................. 185
Fig. 3.3.13 Structure of Interrupt interval determination register ................................................. 186
Fig. 3.3.14 Structure of Interrupt interval determination control register .................................... 186
Fig. 3.3.15 Structure of Port P0 segment/digit switch register..................................................... 187
Fig. 3.3.16 Structure of Port P2 digit/port switch register............................................................. 187
Fig. 3.3.17 Structure of Port P8 segment/port switch register ..................................................... 188
Fig. 3.3.18 Structure of Port PA segment/port switch register ..................................................... 188
Fig. 3.3.19 Structure of FLDC mode register 1 .............................................................................. 189
Fig. 3.3.20 Structure of FLDC mode register 2 .............................................................................. 190
Fig. 3.3.21 Structure of FLD data pointer ....................................................................................... 191
Fig. 3.3.22 Structure of FLD data pointer reload register............................................................. 191
Fig. 3.3.23 Structure of Zero cross detection control register...................................................... 192
Fig. 3.3.24 Structure of Interrupt edge selection register ............................................................. 192
Fig. 3.3.25 Structure of CPU mode register.................................................................................... 193
Fig. 3.3.26 Structure of Interrupt request register 1 ...................................................................... 193
Fig. 3.3.27 Structure of Interrupt request register 2 ...................................................................... 194
Fig. 3.3.28 Structure of Interrupt control register 1 ....................................................................... 194
Fig. 3.3.29 Structure of Interrupt control register 2 ....................................................................... 195
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