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參數資料
| 型號： | M38039M4-XXXKP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數： | 44/119頁 |
| 文件大?。?/td> | 1575K |
| 代理商： | M38039M4-XXXKP |
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 44 of 117
3803 Group (Spec.L)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in a memory. Since the
shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer register, and receive data is
read from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig 38. Block diagram of UART serial I/O1
Fig 39. Operation of UART serial I/O1
f(X
IN
)
1/4
OE
PE
FE
1/16
1/16
Data bus
Data bus
Receive buffer register 1
Address 0018
16
Receive shift register 1
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Address 001C
16
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Transmit buffer register 1
Transmit shift register 1
Address 0018
16
Transmit shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address 0019
16
ST detector
SP detector
UART1 control register
Address 001B
16
Character length selection bit
Address 001A
16
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O1 synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O1 status register
Serial I/O1 control register
P4
6
/S
CLK1
P4
4
/R
X
D
1
P4
5
/T
X
D
1
(f(X
CIN
) in low-speed mode)
TBE=1
RBF=0
TBTSC=0
TBE=0
RBF=1
RBF=1
TBE=1
TSC=1*
ST
D
0
D
1
SP
D
0
D
1
ST
SP
rTransmit or
Transmit buffer
write signal
Serial T
X
D
1
Receive buffer
read signal
Serial input
R
X
D
1
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
ST
D
0
D
1
SP
D
0
D
1
ST
SP
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| M38039M5L-XXXSP | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V |
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