參數(shù)資料
型號(hào)： M38039FFSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-64
文件頁數(shù)： 117/136頁
文件大?。?/td> 2007K
代理商： M38039FFSP
81
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 77 Address data communication format
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I2C control register (S1D: address 001416) to “0”. The first 7-
bit address data transmitted from the master is compared with
the high-order 7-bit slave address stored in the I2C slave ad-
dress register. At the time of this comparison, address
comparison of the RWB bit of the I2C slave address register is
not performed. For the data transmission format when the 7-bit
addressing format is selected, refer to Figure 77, (1) and (2).
10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I2C control register (S1D: address 001416) to “1.” An ad-
dress comparison is performed between the first-byte address
data transmitted from the master and the 8-bit slave address
stored in the I2C slave address register. At the time of this com-
parison, an address comparison between the RWB bit of the
I2C slave address register and the R/W bit which is the last bit
of the address data transmitted from the master is made. In the
10-bit addressing mode, the RWB bit which is the last bit of the
address data not only specifies the direction of communication
for control data, but also is processed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I2C status register (S1: address 001316) is
set to “1.” After the second-byte address data is stored into the
I2C data shift register (S0: address 001116), perform an ad-
dress comparison between the second-byte data and the slave
address by software. When the address data of the 2 bytes
agree with the slave address, set the RWB bit of the I2C slave
address register to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are re-
ceived after a RESTART condition is detected, with the value of
the I2C slave address register. For the data transmission for-
mat when the 10-bit addressing format is selected, refer to
Figure 77, (3) and (4).
S
Slave addressR/W
A
Data
A/A
P
A
Data
7 bits
“0”
1 to 8 bits1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
P
A
Data
7 bits
“1”
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
7 bits
“0”
8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
1 to 8 bits
S
R/W
A
Slave address
1st 7 bits
Slave address
2nd bytes
A
AData
Data
P
A/A
7 bits
“0”
8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
7 bits
“1”
1 to 8 bits1 to 8 bits
S
R/W
A
Slave address
1st 7 bits
Slave address
2nd bytes
A
Sr
Slave address
1st 7 bits
R/W
A
Data
P
A
: Master to slave
: Slave to master
A
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