參數(shù)資料
型號: M38039FFSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PDIP64
封裝: 0.750 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-64
文件頁數(shù): 111/136頁
文件大?。?/td> 2007K
代理商: M38039FFSP
76
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I2C status
register (S1: address 001316) at the same time after writing the
slave address to the I2C data shift register (S0: address 001116)
with the condition in which the ES0 bit of the I2C control register
(S1D: address 001416) is “1” and the BB flag is “0”, a START con-
dition occurs. After that, the bit counter becomes “0002” and an
SCL for 1 byte is output. The START condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 70, the START condition generating timing
diagram, and Table 12, the START condition generating timing
table.
STOP Condition Generating Method
When the ES0 bit of the I2C control register (S1D: address
001416) is “1,” write “1” to the MST and TRX bits, and write “0” to
the BB bit of the I2C status register (S1: address 001316) simulta-
neously. Then a STOP condition occurs. The STOP condition
generating timing is different in the standard clock mode and the
high-speed clock mode. Refer to Figure 71, the STOP condition
generating timing diagram, and Table 13, the STOP condition gen-
erating timing table.
Fig. 70 START condition generating timing diagram
Fig. 71 STOP condition generating timing diagram
Table 13 STOP condition generating timing table
Item
Setup time
Hold time
Standard clock mode
5.0
s (20 cycles)
4.5
s (18 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
High-speed clock mode
3.0
s (12 cycles)
2.5
s (10 cycles)
Table 12 START condition generating timing table
Item
Setup time
Hold time
Standard clock mode
5.0
s (20 cycles)
5.0
s (20 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
High-speed clock mode
2.5
s (10 cycles)
2.5
s (10 cycles)
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
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