參數(shù)資料
型號： M38039FFSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-64
文件頁數(shù)： 114/136頁
文件大?。?/td> 2007K
代理商： M38039FFSP
79
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[I2C Special Mode Status Register (S3)]
001216
The I2C special mode status register (S3: address 001216) con-
sists of the flags indicating I2C operating state in the I2C special
mode, which is set by the I2C special mode control register (S3D:
address 001716).
The stop condition flag is valid in all operating modes.
Bit 0: Slave address 0 comparison flag (AAS0)
Bit 1: Slave address 1 comparison flag (AAS1)
Bit 2: Slave address 2 comparison flag (AAS2)
These flags indicate a comparison result of address data. These
flags are valid only when the slave address control bit (MSLAD) is
“1”.
In the 7-bit addressing format of the slave reception mode, the re-
spective slave address i (i = 0, 1, 2) comparison flags
corresponding to the I2C slave address registers 0 to 2 are set to
“1” when an address data immediately after an occurrence of a
START condition agrees with the high-order 7-bit slave address
stored in the I2C slave address registers 0 to 2 (addresses 0FF716
to 0FF916).
In the 10-bit addressing format of the slave mode, the respective
slave address i (i = 0, 1, 2) comparison flags corresponding to the
I2C slave address registers are set to “1” when an address data is
compared with the 8 bits consisting of the slave address stored in
the I2C slave address registers 0 to 2 and the RWB bit, and the
first byte agrees.
These flags are initialized to “0” at reset, when the slave address
control bit (MSLAD) is “0”, or when writing data to the I2C data
shift register (S0: address 001116).
Bit 5: SCL pin low hold 2 flag (PIN2)
When the ACK interrupt control bit (ACKICON) and the ACK clock
bit (ACK) are “1”, this flag is set to “0” in synchronization with the
falling of the data’s last SCL clock, just before the ACK clock. The
SCL pin is simultaneously held low, and the I2C interrupt request
occurs.
This flag is initialized to “1” at reset, when the ACK interrupt con-
trol bit (ACKICON) is “0”, or when writing “1” to the SCL pin low
hold 2 flag set bit (PIN2IN).
The SCL pin is held low when either the SCL pin low hold bit (PIN)
or the SCL pin low hold 2 flag (PIN2) becomes “0”. The low hold
state of the SCL pin is released when both the SCL pin low hold
bit (PIN) and the SCL pin low hold 2 flag (PIN2) are “1”.
Bit 7: Stop condition flag (SPCF)
This flag is set to “1” when a STOP condition occurs.
This flag is initialized to “0” at reset, when the I2C-BUS interface
enable bit (ES0) is “0”, or when writing “1” to the STOP condition
flag clear bit (SPFCL).
Fig. 75 Structure of I2C special mode status register
b7
b0
I2C special mode status register
(S3 : address 001216)
Slave address 0 comparison flag
0 : Address disagreement
1 : Address agreement
STOP condition flag
0 : No detection
1 : Detection
AAS0
AAS1
AAS2
PIN2
SPCF
Slave address 1 comparison flag
0 : Address disagreement
1 : Address agreement
Slave address 2 comparison flag
0 : Address disagreement
1 : Address agreement
Not used
(return “0” when read)
Not used
(return “0” when read)
SCL pin low hold 2 flag
0 : SCL pin low hold
1 : SCL pin low release (Note)
Note: In order that the low hold state of the SCL pin may release, it is
necessary that the SCL pin low hold 2 flag and the SCL pin low
hold bit (PIN) are “1” simultaneously.
Not used
(return “0” when read)
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