
7905 Group User’s Manual Rev.1.0
20-39
APPENDIX
Appendix 2. Control registers
0
1
7 to 2
Bit name
Bit
Function
At reset
R/W
D-A0 output enable bit
D-A1 output enable bit
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
0
Undefined
RW
—
D-A control register (Address 9616)
Notes 1: Pin DAi is multiplexed with an analog input pin or serial input/output pin. When a D-Ai output enable bit = “1” (in other words,
output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/output pin (including a
programmable I/O port pin).
2: When not using the D-A converter, be sure to clear this bit to “0.”
0
7 to 0
Bit
D-A register i (i = 0 and 1) (Addresses 9816 and 9916)
Function
At reset
R/W
Any value in the range from 0016 through FF16 can be set (Note), and this
value will be D-A converted and will be output.
RW
b0
b7
Reference
13-3
Reference
13-3
Note: When not using the D-A converter, be sure to clear the contents of these bits to “0016.”
0
1
2
3
4
5
7, 6
RY/BY status bit
CPU reprogramming mode select bit
The value is “0” at reading.
Flash memory reset bit (Note 3)
The value is “0” at reading.
User ROM area select bit
(Valid in boot mode)
(Note 5)
The value is “0” at reading.
RO
RW
(Notes 1, 2)
—
RW
(Note 4)
—
RW
(Note 2)
—
1
0
Bit name
Bit
Flash memory control register (Address 9E16)
Function
At reset
R/W
b7 b6 b5 b4 b3 b2 b1 b0
0 : BUSY (Automatic programming or erase operation
is active.)
1 : READY (Automatic programming or erase operation
has been completed.)
0 : Flash memory CPU reprogramming mode is invalid.
1 : Flash memory CPU reprogramming mode is valid.
Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.”
2: Writing to this bit must be performed in an area other than the internal flash memory.
3: This bit is valid when the CPU reprogramming mode select bit (bit 1) = “1”: on the other hand, when the CPU
reprogramming mode select bit = “0,” be sure to fix this bit to “0.” Rewriting of this bit must be performed with the CPU
reprogramming mode select bit = “1.”
4: After writing of “1” to this bit, be sure to confirm the RY/BY status bit (bit 0) becomes “1”; and then, write “0” to this bit.
5: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”)
0 : Access to boot ROM area
1 : Access to user ROM area
Writing “1” into this bit discontinues the access to the
internal flash memory. This causes the built-in flash
memory circuit being reset.
Reference
19-10
19-11