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THREE-PHASE WAVEFORM MODE
7905 Group User’s Manual Rev.1.0
10-4
10.2 Block description
Figure 10.2.1 shows the block diagram of the three-phase waveform mode, and explanation of registers
relevant to the three-phase waveform mode is described below.
The following registers are common to pulse output port 0 and three-phase waveform mode:
Waveform output mode register (address A616)
Three-phase output data register 0 (address A816)
Three-phase output data register 1 (address A916)
When using the three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 through
0 at address A616) to “1002,” and then, set the relevant registers.
When not using pulse output port 0 and three-phase waveform mode, be sure to fix the waveform output
select bits (bits 2 through 0 at address A616) to “0002.”
10.2 Block description
Fig. 10.2.1 Block diagram of three-phase waveform mode
DQ
T
D
Q
Output
polarity
set
toggle
flip-flop
2
“0
”
“1
”
D
Q
T
R
Timer
A3
(16)
(Timer
mode)
Timer
A2
Reload
Timer
A2
1
Timer
A2
counter
(16)
U-phase
output
polarity
set
buffer
(bit
5
at
address
A9
16
)
T
Interval
control
D
Q
R
D
Q
R
Timer
A1
Reload
Timer
A1
1
Timer
A1
counter
(16)
V-phase
output
polarity
set
buffer
(bit
4
at
address
A9
16
)
T
Timer
A0
Reload
Timer
A0
1
Timer
A0
counter
(16)
W-phase
output
polarity
set
buffer
(bit
3
at
address
A8
16
)
T
Three-phase
output
polarity
set
buffer
(bit
3
at
address
A6
16
)
Interrupt
validity
output
select
bit
(bit
5
at
address
A9
16
)
Three-phase
mode
select
bit
(bit
4
at
address
A6
16
)
D
Q
Output
polarity
set
toggle
flip-flop
0
“0
”
“1
”
D
Q
Output
polarity
set
toggle
flip-flop
1
“0
”
“1
”
Reset
Interrupt
request
interval
set
bit
(bit
4
at
address
A9
16
)
“1
”
“0
”
Reset
Q
D
R
Reset
Timer
A3
interrupt
request
signal
(One-shot
pulse
mode)
(One-shot
pulse
mode)
(One-shot
pulse
mode)
Reload
register
Dead-time
timer
(8)
T
Dead-time
timer
(8)
T
f2
f4
f8
Clock-source-of-dead-time-timer
select
bits
(bits
7,
6
at
address
A8
16
)
D
Q
T
Dead-time
timer
(8)
T
D
Q
R
Reset
P6OUT
CUT
U
V
W
U
V
W
Waveform
output
control
bit
(bit
7
at
address
A6
16
)
U-phase
output
fix
bit
(bit
2
at
address
A8
16
)
DQ
Trigger
generating
circuit
S
R
Q
T
Q
V-phase
output
fix
bit
(bit
1
at
address
A8
16
)
DQ
T
Trigger
generating
circuit
S
R
Q
T
Q
W-phase
output
fix
bit
(bit
0
at
address
A8
16
)
DQ
T
Trigger
generating
circuit
S
R
Q
T
Q
U-phase
output
control
circuit
V-phase
output
control
circuit
W-phase
output
control
circuit
D
Q
T
D
Q
T
D
Q
T
D
Q
T
D
Q
T
U-phase
output
fix
polarity
set
bit
(bit
2
at
address
A9
16
)
W-phase
output
fix
polarity
set
bit
(bit
0
at
address
A9
16
)
V-phase
output
fix
polarity
set
bit
(bit
1
at
address
A9
16
)
1/2
IDU
T
Q
D
T
Q
D
T
Q
D
b2
IDV
IDW
b1
b0
Databus
(even-numbered)
Bits
2
through
0
of
position-
data-retain
function
control
register
(address
AA
16
)
circuit