參數(shù)資料
型號(hào): M37902FGCGP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁(yè)數(shù): 75/143頁(yè)
文件大?。?/td> 1463K
代理商: M37902FGCGP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)當(dāng)前第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)
75
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
The FERi, PERi, and SUMi flags are cleared to
0
when reading the
low-order byte of the receive buffer register or when writing
0
to the
REi flag.
The OERi flag is cleared to
0
when writing
0
to the REi flag.
Interrupt request at completion of reception
When the RIk flag changes from
0
to
1
, in other words, when the
receive operation is completed, the interrupt request bit of the
UARTk receive interrupt control register can be set to
1
.
The timing when this interrupt request bit is to be set to
1
can be
selected from the following:
Each reception
When an error occurs at reception
If bit 5 of the UARTk transmit/receive control register 0 (UART re-
ceive interrupt mode select bit) is cleared to
0
, the interrupt request
bit is set to
1
at each reception. If bit 5 is set to
1
, the interrupt
request bit is set to
1
only when an error occurs. (In the clock asyn-
chronous serial communication, when an overrun error, framing er-
ror, or parity error occurs, the interrupt request bit is set to
1
.)
Sleep mode
The sleep mode is used to communicate only between certain micro-
computers when multiple microcomputers are connected through
serial I/O.
The microcomputer enters the sleep mode when bit 7 of UARTi
transmit/receive mode register is set to
1.
The operation of the sleep mode for an 8-bit asynchronous commu-
nication is described below.
When sleep mode is selected, the contents of the receive register is
not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asyn-
chronous communication and bit 8 if 9-bit asynchronous communi-
cation) of the received data is
0
. Also the RIi, OERi, FERi, PERi,
and the SUMi flags are unchanged. Therefore, the interrupt request
bit of the UARTi receive interrupt control register is also unchanged.
Normal receive operation takes place when bit 7 of the received data
is
1
.
The following is an example of how the sleep mode can be used.
The main microcomputer first sends data: bit 7 is
1
and bits 0 to 6
are set to the address of the subordinate microcomputer to be com-
municated with. Then all subordinate microcomputers receive this
data. Each subordinate microcomputer checks the received data,
clears the sleep bit to
0
if bits 0 to 6 are its own address and sets
the sleep bit to
1
if not. Next, the main microcomputer sends data
with bit 7 cleared. Then the microcomputer which cleared the sleep
bit will receive the data, but the microcomputers which set the sleep
bit to
1
will not. In this way, the main microcomputer is able to com-
municate only with the designated microcomputer.
Precautions for clock asynchronous (UART)
serial communication
When using pin CTS
0
/RTS
0
, be sure to clear the D-A
2
output enable
bit (bit 2 at address 96
16
) to
0
(output disabled). Also, when CTSi
and RTSi are separated, pin CLKi cannot be used. Therefore, when
CTSi and RTSi are separated in UART mode, be sure to select an
internal clock.
Before transmit operation is performed, be sure to clear bits 2 and 3
of the serial I/O pin control register (address AC
16
) to
00
.
相關(guān)PDF資料
PDF描述
M37902FCCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37902FGCHP DIODE SCHOTTKY DUAL COMMON-ANODE 25V 150mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-523 3K/REEL
M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37905F8CFP 16-BIT CMOS MICROCOMPUTER
M37905F8CSP 16-BIT CMOS MICROCOMPUTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37902FGCHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37902FJCHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37903S4CHP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT CMOS MICROCOMPUTER
M37905F8CFP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16-BIT CMOS MICROCOMPUTER
M37905F8CSP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16-BIT CMOS MICROCOMPUTER