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| 型號(hào)： | M37902FGCGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 68/143頁(yè) |
| 文件大?。?/td> | 1463K |
| 代理商： | M37902FGCGP |
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M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
68
Transmission
Transmission is started when bit 0 (TEj flag: transmit enable bit) of
UARTj transmit/receive control register 1 is
“
1
”
, bit 1 (TIj flag) of one
is
“
0
”
, and CTSj input is
“
L
”
. The TIj flag indicates whether the trans-
mit buffer register is empty or not. It is cleared to
“
0
”
when data is
written in the transmit buffer register ; it is set to
“
1
”
when the con-
tents of the transmit buffer register is transferred to the transmit reg-
ister and the transmit buffer register becomes empty.
When all of the transmit conditions are satisfied, the transmit data in
the transmit buffer register are transferred to the transmit register,
and transmission starts. As shown in Figure 70, data is output from
T
X
Dj pin each time when transmission clock CLKj changes from
“
H
”
to
“
L
”
. (In the clock synchronous serial I/O mode, the polarity of a
transfer clock can be changed. For details, refer to the section on the
selection of the transfer clock polarity.) The data is output from the
least significant bit.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmission start
condition is satisfied. The next transmission is performed
succeedingly. Once transmission has started, the TEj flag, TIj flag,
and CTSj signals are ignored until data transmission completes.
Therefore, transmission is not interrupt when CTSj input is changed
to
“
H
”
during transmission.
CTSj is checked while the T
END
j signal (shown in Figure 70) is
“
H
”
.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIj flag is
cleared to
“
0
”
before theT
END
j signal goes
“
H
”
.
Bit 3 (T
X
EPTYj flag) of UARTj transmit/receive control register 0
changes to
“
1
”
at the next cycle just after the T
END
j signal goes
“
H
”
and changes to
“
0
”
when transmission starts. Therefore, this flag can
be used to determine whether data transmission has completed.
When the TIj flag changes from
“
0
”
to
“
1
”
, the interrupt request bit in
the UARTj transmit interrupt control register is set to
“
1
”
.
Receive
When bit 2 of the UART
k
transmit/receive control register 1 is set to
“
1
”
, reception becomes enabled. In this case, when the CLKk signal
is input, the receive operation starts simultaneously with this signal.
The RTSk output is
“
H
”
when the REK flag is
“
0
”
. When the REK flag
is set to
“
1
”
, the RTSk output becomes
“
L
”
. This informs the transmit-
ter side that reception becomes enabled. When the receive opera-
tion starts, the RTSk output automatically becomes
“
H
”
.
When the receive operation starts, the receiver takes data from pin
RxDk each time when the transmit clock (CLKj) turns from
“
L
”
to
“
H
”
.
Simultaneously with reception, the contents of the receiver register
is shifted bit by bit.
(Note that, in the clock synchronous serial communication, the polar-
ity of a transfer clock can be inverted. For details, refer to the section
on the polarity of the transfer clock.) When an 8-bit data is received,
the contents of the receive register is transferred to the receive buffer
register and bit 3 (RIk flag) of UARTk transmit/receive control regis-
ter 1 is set to
“
1
”
. In other words, the setting
“
1
”
to the RIk flag indi-
cates that the receive buffer register contains the received data. At
this time, if the low-order byte of the UARTk receive buffer register is
read out, the RTSk output turns back to
“
L
”
. This indicates that the
next data reception becomes enabled. Bit 4 (OERk flag) of UARTk
transmit/receive control register 1 is set to
“
1
”
when the next data is
transferred from the receive register to the receive buffer register
while RIk flag is
“
1
”
, and indicates that the next data was transferred
to the receive register before the contents of the receive buffer regis-
ter was read. (In other words, this indicates that an overrun error has
occurred.) RIk flag is automatically cleared to
“
0
”
when the low-order
byte of the receive buffer register is read or when the REk flag is
cleared to
“
0
”
. The OERk flag is cleared when the REk flag is
cleared. Bit 5 (FERk flag), bit 6 (PERk flag), and bit 7 (SUMk flag) are
ignored in clock synchronous mode.
As shown in Figure 64, with clock synchronous serial communica-
tion, data cannot be received unless the transmitter is operating be-
cause the receive clock is created from the transmission clock.
Therefore, the transmitter must be operating even when there is no
need to sent data from UARTk to UARTj.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37902FCCHP | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FGCHP | DIODE SCHOTTKY DUAL COMMON-ANODE 25V 150mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-523 3K/REEL |
| M37902FJCHP | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37905F8CFP | 16-BIT CMOS MICROCOMPUTER |
| M37905F8CSP | 16-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37902FGCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FJCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37903S4CHP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:16-BIT CMOS MICROCOMPUTER |
| M37905F8CFP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:16-BIT CMOS MICROCOMPUTER |
| M37905F8CSP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:16-BIT CMOS MICROCOMPUTER |
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