- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98006 > M37754S4CGP 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | M37754S4CGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 94/117頁 |
| 文件大?。?/td> | 1575K |
| 代理商： | M37754S4CGP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁當(dāng)前第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁
75
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
OUTPUT FUNCTION OF CHIP SELECT SIGNAL
___
Ports P90 to P94 can output the chip select signals CS0 to CS4 ac-
cording to the contents of chip select control register and chip select
area register. Bits 0 to 3 of chip select control register select either
chip select output (or addresses A20 to A22 output) or port function.
Additionally, bits 0 to 2 of chip select area register select the area in-
tended for each chip select signal.
Figure 87 shows the bit configuration of chip select control register
and Figure 88 shows that of chip select area register. Figure 89
shows the chip select areas.
___
The bus cycle of CS3 and CS4 can be selected with bits 4 to 7 of chip
select control register. That selection is valid regardless of the bus
cycle select bits of processor mode register 1. Additionally, that bus
___
cycle selection of CS3 and CS4 is valid when selecting port function
___
with the CS3 and CS4 function select bits.
When accessing addresses in which the chip select area specified
by bits 0 to 2 of chip select area register and the internal memory
area overlap one another, chip select signals are not output. In this
case, its bus cycle is the cycle of internal memory area access.
It is possible to make the chip select output floating during Hold
state. That is realized by clearing the corresponding bit of port P9
direction register (address 1516) to “0” and bits 0 to 2 of waveform
output mode register (address 1A16) to “000”. The timing of Hold
start and termination is the same as that of addresses A0 to A19. (Re-
fer to section on processor mode.)
ADDRESS OUTPUT FUNCTION
Port P91 to P93 can output the high-order addresses (A20 to A22) ac-
cording to bits 1 and 2 of chip select control register, and bits 6 and 7
of chip select area register.
___
About signal pairs of A20 and CS1, A21 and CS2, and A22 and CS3,
___
only one signal can be output. It is because chip select signals CS1
___
to CS3 output are common to ports P91 to P93 and addresses A20 to
A22 output.
It is possible to make the address output floating during Hold state.
That is realized by clearing the corresponding bit of port P9 direction
register (address 1516) to “0” and bits 0 to 2 of waveform output
mode register (address 1A16) to “000”. The timing of Hold start and
termination is the same as that of addresses A0 to A19. (Refer to sec-
tion on processor mode.)
Fig. 87 Chip select control register bit configuration
Address
6216
CS0 function select bit (Note 1)
0 : Port P90 function
1 : CS0 output
CS4 function select bit
0 : Port P94 function
1 : CS4 output
CS1, CS2 function select bit (Note 2)
0 : Port P91, P92 function
1 : CS1, CS2 output or A20, A21 output
CS3 function select bit (Note 2)
0 : Port P93 function
1 : CS3 output or A22 output
76543210
CS3 bus cycle select bits
b5 b4 In high-speed In low-speed
0 0 : 5-
φ access
Do not select.
0 1 : 4-
φ access
4-
φ access
1 0 : 3-
φ access
3-
φ access
1 1 : Do not select. 2-
φ access
CS4 bus cycle select bits
b7 b6 In high-speed In low-speed
0 0 : 5-
φ access
Do not select.
0 1 : 4-
φ access
4-
φ access
1 0 : 3-
φ access
3-
φ access
1 1 : Do not select. 2-
φ access
Notes 1 : At reset, bit 0 becomes “0” when the CNVss pin’s level is “L”;
bit 0 becomes “1” when the CNVss pin’s level is “H”.
2 : Bits 6 and 7 of chip select area register (address 6316) specify
whether the chip select signal or address is output.
Chip select control register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37754S4CHP | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| M37902FCCHP | 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100 |
| M37902FGCHP | 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100 |
| M37906F8CSP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDIP42 |
| M37906F8CFP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37754S4CHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M3775PR-H400CL | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-0.75A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-C0.50A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-C0.50B | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。