參數資料
型號: M37754S4CGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數: 2/117頁
文件大?。?/td> 1575K
代理商: M37754S4CGP
7
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37754M8C-XXXGP contains the following devices on a single
chip: ROM, RAM, CPU, bus interface unit, timers, UART, A-D con-
verter, D-A converter, I/O ports, clock generating circuit and others.
Each of these devices is described below.
MEMORY
The memory map is shown in Figure 1. The address space is 16
Mbytes from addresses 016 to FFFFFF16. The address space is di-
vided into 64-Kbyte units called banks. The banks are numbered
from 016 to FF16.
Internal ROM, internal RAM, and control registers for internal periph-
eral devices are assigned to bank 016.
The 60-Kbyte area from addresses 100016 to FFFF16 is the internal
ROM.
Addresses FFD216 to FFFF16 are the RESET and interrupt vector
addresses and contain the interrupt vectors. Refer to the section on
interrupts for details.
The 2048-byte area from addresses 8016 to 87F16 contains the inter-
nal RAM. In addition to storing data, the RAM is used as stack during
a subroutine call, or interrupts.
Assigned to addresses 016 to 7F16 are peripheral devices such as
I/O ports, A-D converter, D-A converter, UART, timer, and interrupt
control registers.
Additionally the internal ROM area can be modified by software.
Refer to the section on ROM area modification function for details.
A 256-byte direct page area can be allocated anywhere in bank 016
using the direct page register DPR. In direct page addressing mode,
the memory in the direct page area can be accessed with two words
thus reducing program steps.
Note: Internal ROM area can be modified. (Refer to the section on ROM area modification function.)
00000016
00007F16
00087F16
00FFFF16
00FFFE16
00FFD216
00008016
00FFFF16
Bank 016
Bank 116
01000016
01FFFF16
FF000016
FFFFFF16
Internal RAM
2048 bytes
Peripherai devices
control registers
Interrupt vector table
A–D
INT3
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2
Watchdog timer
BRK instruction
Zero divide
see Fig. 2 for
further information
INT1
INT0
DBC
RESET
Bank FF16
Internal ROM
60 Kbytes
00100016
FE000016
FEFFFF16
Bank FE16
00007F16
INT4
Fig. 1 Memory map
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