DMA CONTROLLER
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13.7 Array chain transfer mode
7721 Group User’s Manual
b7
b0
Selection of transfer mode and each function
b7
b0
0
b7
b0
0
1
From preceding “Figure 13.7.3”
b7
b0
b0 b7
b7
(b23)
(b8)
(b16) (b15)
Set the start address of transfer parameter memory.
These bits can be set to “00000016” to “FFFFFF16.”
b7
b0
b0 b7
b7
(b23)
(b8)
(b16) (b15)
DMA0 mode register L (Address 1FCC16)
DMA1 mode register L (Address 1FDC16)
DMA2 mode register L (Address 1FEC16)
DMA3 mode register L (Address 1FFC16)
Number-of-unit-transfer-bits select bit
0 : 16 bits
1 : 8 bits
Transfer method select bit
0 : 2-bus cycle transfer
1 : 1-bus cycle transfer
Transfer mode select bit
0 : Burst transfer mode
1 : Cycle-steal transfer mode
Transfer source address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
Transfer destination address direction select bits
0 0 : Fixed
0 1 : Forward
1 0 : Backward
1 1 : Do not select.
DMA0 mode register H (Address 1FCD16)
DMA1 mode register H (Address 1FDD16)
DMA2 mode register H (Address 1FED16)
DMA3 mode register H (Address 1FFD16)
Transfer direction select bit (Used in 1-bus cycle transfer)
0 : From memory to I/O
1 : From I/O to memory
I/O connection select bit (Valid in 1-bus cycle transfer)
0 : Data bus D0–D7 or D0–D15
1 : Data bus D8–D15
Transfer source wait bit (Valid in DMA transfer)
0 : Wait
1 : No wait
Transfer destination wait bit (Valid in DMA transfer)
0 : Wait
1 : No wait
Selection of array chain transfer mode
Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0)
Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1)
Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2)
Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3)
Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0)
Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1)
Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2)
Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3)
Set the number of transfer blocks.
These bits can be set to “00000116” to “FFFFFF16.”
Notes 1: When writing to these registers,
write to all 24 bits.
2: Do not write “00000016” to TCRi.
DMA0 control register (Address 1FCE16)
DMA1 control register (Address 1FDE16)
DMA2 control register (Address 1FEE16)
DMA3 control register (Address 1FFE16)
0 0 0 0 : Do not select.
0 0 0 1 : External source (DMAREQi)
0 0 1 0 : Software DMA source
0 0 1 1 : Timer A0
0 1 0 0 : Timer A1
0 1 0 1 : Timer A2
0 1 1 0 : Timer A3
0 1 1 1 : Timer A4
1 0 0 0 : Timer B0
1 0 0 1 : Timer B1
1 0 1 0 : Timer B2
1 0 1 1 : UART0 receive
1 1 0 0 : UART0 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : UART1 transmit
1 1 1 1 : A-D conversion
Edge sense/Level sense select bit (Note)
0 : Edge sense
1 : Level sense
DMAACKi validity bit
0 : Invalid
1 : Valid
Note: When an external source (DMAREQi)
is selected or when the cycle-steal
transfer mode is selected, set this bit
to “0.”
Continue to “Figure 13.7.5” on next page.
DMA request source select bits
Fig. 13.7.4 Initial setting example for registers relevant to array chain transfer mode (2)