
7721 Group User’s Manual
13-10
DMA CONTROLLER
Fig. 13.2.4 Structure of DMAC control register L
13.2 Block description
13.2.2 DMAC control register L
Figure 13.2.4 shows the structure of DMAC control register L. Bit 0 is described in section “13.3.3 Channel
priority levels,” and bits 4–7 are also in section “13.3.2 DMA requests.”
(1)
___
TC
pin validity bit (Bit 1)
___
When this bit is set to “1,” port P103 functions as the TC pin. The TC pin is of an N-channel open-
drain type and provides the following functions:
q Terminal count signal output
When the transfer of an entire batch of data is normally terminated, the pin outputs “L” for 1
cycle of
φ. (Refer to section “13.3.5 (1) Normal termination.”)
q Forced termination signal input
___
When the TC pin’s input level goes from “H” to “L” during DMA transfer, this DMA transfer is forced
into termination. (Refer to section “13.3.5 (2) Forced termination.”)
Notes 1: The state of bits 4 to 7 is not changed when writing “1” to these bits.
2: When writing to this register while any of DMAi enable bits (bits 4 to 7 at address
6916) is “1,” use the LDM or STA instruction in m flag = “1.” When DMAi request bit
(bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to “1.”
When writing to this register while all of DMAi enable bits (bits 4 to 7 at address 6916)
are “0,” m flag may be “0” or “1.” Use the LDM or STA instruction for writing to this
register. When DMAi request bit (bits 4 to 7 at address 6816) must not be changed,
set DMAi request bit to “1.”
0 : Fixed
1 : Rotating
Bit
Bit name
Functions
At reset
RW
0
1
Priority select bit
Undefined
0
0 : No request
1 : Requested (Note 1)
0
DMAC control register L (Address 6816)
b1
b0
b2
b3
b4
b5
b6
b7
RW
3, 2
0
RW
0
RW
TC pin validity bit
0 : Invalid
(P103 pin functions as a
programmable I/O port (CMOS).)
1 : Valid
(P103 pin functions as TC pin (N-
channel open-drain).)
Nothing is assigned.
–
4
5
6
7
DMA0 request bit
DMA1 request bit
DMA2 request bit
DMA3 request bit
0RW
0
RW