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參數(shù)資料
| 型號： | M37640M4T |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 563K |
| 代理商： | M37640M4T |
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MITSUBISHI
ELECTRIC
24
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 22
Timer 123 mode register configuration (
φ
is internal system clock)
Operating Modes
(1) Timer Mode
This mode is available with timers 1 to 3.
Count source
For timer 1, the count source is the output of the corresponding
pre-divider. For timers 2 and 3, the count source can be sepa-
rately selected to be either the pre-divider output or timer 1
underflow.
Operation
The timer counts down. On a timer underflow, the corresponding
timer interrupt request bit will be set to “1”, the contents of the
corresponding timer latch will be reloaded to the counter and
counting continues.
(2) PWM Mode
This mode is available with timer 2 and 3.
Count source
The count source can be separately selected to be either the
pre-divider output or timer 1 underflow.
Operation
When the PWM-mode is enabled, timer 2 starts counting. As
soon as timer 2 underflows, timer 2 stops and timer 3 starts
counting. If bit 0 is set, timer 2 determines the low duration and
the initial output level is low. Timer 3 determines the high dura-
tion. If bit 0 is zero timer 2 determines the high duration and the
initial output level is high. In this case timer 3 determines the low
duration.
Note: Be sure to configure the P1
6
/PWM pin as an output port
before using PWM mode.
PWM polarity selection bit
0 :
Start on “H” level output
1 :
Start on “L” level output
PWM output enable bit
0 :
PWM output disabled
1 :
PWM output enabled
Timer 2 write control bit
0 :
Latch and counter
1 :
Latch only
Timer 2 count source selection bit
0 :
Timer 1 underflow
1 :
Pre-divider output
Timer 3 count source selection bit
0 :
Timer 1 underflow
1 :
Pre-divider output
Not used (“0” when read, do not write “1”)
Pre-divider division ratio bits
b7 b6
0 0:
φ
divided by 1
0 1:
φ
divided by 8
1 0:
φ
divided by 32
1 1:
φ
divided by 128
7
0
Timer 123 mode register (address 0019
16
)
T123M
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