參數(shù)資料
型號(hào)： M37640M4T
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 21/48頁(yè)
文件大?。?/td> 563K
代理商： M37640M4T
MITSUBISHI MICROCOMPUTERS
7630 Group
21
MITSUBISHI
ELECTRIC
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 19
Operating Modes
(1) Timer mode
This mode is available with timer X and timer Y.
Count source
The count source for timer X and Y is the output of the corre-
sponding clock divider. The division ratio can be selected by the
timer Y mode register.
Operation
Both timers X and Y are down counters. On a timer underflow,
the corresponding timer interrupt request bit will be set to “1”, the
contents of the corresponding timer latches will be reloaded to
the counters and counting continues.
(2) Bi-phase counter mode (quadruplicate)
This mode is available with timer X only.
Count source
The count sources are P1
4
/CNTR
0
and the P1
3
/TX
0
pins.
Operation
Timer X will count both rising and falling edges on both input pins
(see above). Refer to Timer X bi-phase counter mode operation
for the timing chart of the bi-phase counter mode.
Structure of timer Y mode register (
φ
is internal system clock)
The count direction is determined by the edge polarity and level
of count source inputs and may change during the count opera-
tion. Refer to the table below.
On a timer over- or underflow, the corresponding interrupt
request bit will be set to “1” and counting continues.
Timer X count source selection bits
b1 b0
0 0:
φ
divided by 4
0 1:
φ
divided by 16
1 0:
φ
divided by 64
1 1:
φ
divided by 128
Timer Y count source selection bits
b3 b2
0 0:
φ
divided by 2
0 1:
φ
divided by 8
1 0:
φ
divided by 32
1 1:
φ
divided by 64
Timer Y operation mode bits
b5 b4
0 0: Timer mode
0 1: Pulse period measurement mode
1 0: Event counter mode
1 1: H/L pulse width measurement mode
CNTR
1
polarity selection bit
0 :
For event counter mode, rising edge active
For interrupt request, falling edge active
For pulse period measurement mode, refer to falling edges
1 :
For event counter mode, falling edge active
For interrupt request, rising edge active
For pulse period measurement mode, refer to rising edges
Timer Y stop control bit
0 :
Timer counting
1 :
Timer stopped
7
0
Timer Y mode register (address 001F
16
)
TYM
Table 4: Timer X count direction in Bi-phase counter mode
P1
3
/TX
0
P1
4
/CNTR
0
Count direction
↑
Edge
L
Up
H
Down
↓
Edge
L
Down
H
Up
L
↑
Edge
Down
H
Up
L
↓
Edge
Up
H
Down
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