參數(shù)資料
型號(hào): M37630E4T-XXXFS
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù): 37/48頁(yè)
文件大?。?/td> 563K
代理商: M37630E4T-XXXFS
MITSUBISHI MICROCOMPUTERS
7630 Group
37
MITSUBISHI
ELECTRIC
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer consists of two separate counters: one 7-bit
counter (WD
H
) and one 4-bit counter (WD
L
). Cascading both
counters or using the high-order counter allows only to select the
time-out from either 524288 or 32768 cycles of the internal clock
φ
.
Refer to Fig. 41 and Fig. 42. Both counters are addressed by the
same watchdog timer register (WDT). When writing to this register,
both counters will be set to the following default values:
the high-order counter will be set to address 7F
16
the low-order counter will be set to address F
16
regardless of the data written to the WDT register. Reading the
watchdog timer register will return the corresponding control bit sta-
tus, not the counter contents.
Once the WDT register is written to, the watchdog timer starts
counting down and the watchdog timer interrupt is enabled. Once it
is running, the watchdog timer cannot be disabled or stopped
except by reset. On a watchdog timer underflow, a non-maskable
watchdog timer interrupt will be requested.
To prevent the system being stopped by STP instruction, this
instruction can be disabled by the STP instruction disable bit of
WDT register. Once the STP instruction is disabled, it cannot be
enabled again except by RESET.
Fig. 41
Block diagram of watchdog timer
Fig. 42
Structure of watchdog timer register (
φ
is internal clock system)
1/256
φ
WDT interrupt
WD
L
counter (4)
WD
H
counter (7)
WDT
7
“F
16
“7F
16
WDT register (8)
“0”
“1”
Not used (undefined when read)
Stop instruction disable bit
0 :
Stop instruction enabled
1 :
Execute two NOP instructions instead (once this bit is set to
“1” it can not be cleared to “0” again, except on RESET.)
Upper byte count source selection bit
0 :
Underflow of the low order counter
1 :
φ
divided by 256
7
0
Watchdog timer register (address 002E
16
)
WDT
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