參數(shù)資料
型號(hào)： M37630E4T-XXXFS
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 14/48頁(yè)
文件大?。?/td> 563K
代理商： M37630E4T-XXXFS
MITSUBISHI
ELECTRIC
14
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
There are 24 interrupts: 6 external, 17 internal, and 1 software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an
interrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs when the correspond-
ing interrupt request and enable bits are “1” and the interrupt dis-
able flag is “0”. Interrupt enable bits can be cleared or set by
software. Interrupt request bits can be cleared by software but can-
not be set by software. The BRK instruction interrupt and reset can-
not be disabled with any flag or bit. The I flag disables all interrupts
except the BRK instruction interrupt and reset. If several interrupt
requests occur at the same time, the interrupt with the highest prior-
ity is accepted first.
Interrupt Operation
Upon acceptance of an interrupt, the following operations are auto-
matically performed.
1.
The processing being executed is stopped.
2.
The contents of the program counter and processor status
register are automatically pushed onto the stack.
Concurrently with the push operation, the interrupt jump
destination address is read from the vector table into the
program counter.
The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
Notes on use
When the active edge of an external interrupt (INT
0
, INT
1
, CNTR
0
,
CNTR
1
, CWKU or KOI) is changed, the corresponding interrupt
request bit may also be set. Therefore, take the following sequence.
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register.
(in the case of CNTR
0
: Timer X mode register; in the case of
CNTR
1
: Timer Y mode register)
(3) Clear the interrupt request bit to “0”.
(4) Enable the external interrupt which is selected.
3.
4.
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