參數(shù)資料
型號: M37630E4T-XXXFS
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 25/48頁
文件大?。?/td> 563K
代理商: M37630E4T-XXXFS
MITSUBISHI MICROCOMPUTERS
7630 Group
25
MITSUBISHI
ELECTRIC
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/Os
The serial I/O section of 7630 group consists of one clock synchro-
nous and one asynchronous (UART) interface.
Clock Synchronous Serial I/O (SI/O)
The clock synchronous interface allows full duplex communication
based on 8 bit word length. The transfer clock can be selected from
an internal or external clock. When an internal clock is selected, a
programmable clock divider allows eight different transmission
speeds. Refer to Block diagram of clock synchronous I/O (f is inter-
nal system clock). The operation of the clock synchronous serial I/O
can be configured by the serial I/O control register SIOCON; refer to
Fig. 25.
Fig. 23
Block diagram of clock synchronous I/O (
φ
is internal system clock)
(1) Clock synchronous serial I/O operation
Either an internal or external transfer clock can be selected by bit 6
of SIOCON. The internal clock divider can be programmed by bits 0
to 2 of SIOCON. Bit 3 of SIOCON determines whether the double
function pins P2
0
to P2
2
will act as I/O ports or serve as SIO pins.
Bit 4 of SIOCON allows the same selection for pin P2
3
.
When an internal transfer clock is selected, transmission can be
triggered by writing data to the SI/O shift register (SIO, address
0012
16
). After an 8–bit transmission has been completed, the S
OUT
pin will change to high impedance and the SIO interrupt request bit
will be set to “1”.
When an external transfer clock is selected, the SIO interrupt
request bit will be set to “1” after 8 cycles but the contents of the
SI/O shift register continue to be shifted while the transfer clock is
being input. Therefore, the clock needs to be controlled externally;
the S
OUT
pin will not change to high impedance automatically.
SIOCON
2, 1, 0
φ
SIO interrupt
Sync. circuit
P2
3
latch
P2
2
/S
CLK
P2
3
/S
RDY
P2
2
latch
SIO counter (3)
P2
1
/S
OUT
P2
1
latch
SIO shift register (8)
P2
0
/S
IN
P2
0
latch
SIOCON
4
SIOCON
3
SIOCON
3
SIOCON
3
SIOCON
6
Clock divider
“0”
“1”
“0”
“0”
“0”
“0”
“1”
“1”
“1”
“1”
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