參數(shù)資料
型號: M37540E8GP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 37/64頁
文件大小: 668K
代理商: M37540E8GP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7540 Group
MITSUBISHI MICROCOMPUTERS
37
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
tween X
IN
and X
OUT
, and an RC oscillation circuit can be formed by
connecting a resistor and a capacitor.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values. No external resistor is needed
between X
IN
and X
OUT
since a feed-back resistor exists on-chip.
Set the constants of the resistor and capacitor when an RC oscillator
is used, so that a frequency variation due to LSI variation and resis-
tor and capacitor variations may not exceed the standard input fre-
quency.
G
Oscillation control
Stop mode
When the STP instruction is executed, the internal clock f stops at
an “H” level and the X
IN
oscillator stops. At this time, timer 1 is set
to “01
16
” and prescaler 1 is set to “FF
16
” when the oscillation stabi-
lization time set bit after release of the STP instruction is “0”. On the
other hand, timer 1 and prescaler 1 are not set when the above bit
is “1”. Accordingly, set the wait time fit for the oscillation stabiliza-
tion time of the oscillator to be used. f(X
IN
)/16 is forcibly connected
to the input of prescaler 1. When an external interrupt is accepted,
oscillation is restarted but the internal clock f remains at “H” until
timer 1 underflows. As soon as timer 1 underflows, the internal
clock f is supplied. This is because when a ceramic oscillator is
used, some time is required until a start of oscillation. In case oscil-
lation is restarted by reset, no wait time is generated. So apply an
“L” level to the RESET pin while oscillation becomes stable.
Also, the STP instruction cannot be used while CPU is operating by
a ring oscillator.
Wait mode
If the WIT instruction is executed, the internal clock f stops at an “H”
level, but the oscillator does not stop. The internal clock restarts if
a reset occurs or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted. To ensure that interrupts will be received to
release the STP or WIT state, interrupt enable bits must be set to
“1” before the STP or WIT instruction is executed.
When the STP status is released, prescaler 1 and timer 1 will start
counting clock which is X
IN
divided by 16, so set the timer 1 inter-
rupt enable bit to “0” before the STP instruction is executed.
Note
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler
1 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
G
Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting a built-in ring
oscillator. Then, a ceramic oscillation or an RC oscillation is selected
by setting bit 5 of the CPU mode register.
G
Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can be
used. Do not use it when an RC oscillation is selected.
G
CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In order
to prevent the dead-lock by error-writing (ex. program run-away), these
bits can be rewritten only once after releasing reset. After rewriting it
is disable to write any data to the bit. (The emulator MCU
“M37540RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
G
Clock division ratio, X
IN
oscillation control,
ring oscillator control
The state transition shown in Fig. 49 can be performed by setting the
clock division ratio selection bits (bits 7 and 6), X
IN
oscillation control
bit (bit 4), ring oscillator oscillation control bit (bit 3) of CPU mode
register. Be careful of notes on use in Fig. 49.
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