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參數(shù)資料
| 型號： | M37540 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits CMOS Microcomputer(8位單片機) |
| 中文描述： | 單芯片的CMOS 8位單片機（8位單片機） |
| 文件頁數(shù)： | 19/64頁 |
| 文件大?。?/td> | 668K |
| 代理商： | M37540 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7540 Group
MITSUBISHI MICROCOMPUTERS
19
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
G
Timer X
Timer X can be selected in one of 4 operating modes by setting the
timer X mode register.
Timer Mode
The timer counts the signal selected by the timer X count source
selection bits.
Pulse Output Mode
The timer counts the signal selected by the timer X count source
selection bits, and outputs a signal whose polarity is inverted each
time the timer value reaches “0”, from the CNTR
0
pin.
When the CNTR
0
active edge switch bit is “0”, the output of the
CNTR
0
pin is started with an “H” output. At “1”, this output is started
with an “L” output. When using a timer in this mode, set the port
P1
4
direction register to output mode. Also, in the pulse output
mode, the inverted waveform of pulse output from CNTR
0
pin can
be output from TX
OUT
pin by setting the P0
3
/TX
OUT
output valid
bit to “1” . When using a timer in this mode, set the port P0
3
direc-
tion register to output mode.
Event Counter Mode
The operation in the event counter mode is the same as that in
the timer mode except that the timer counts the input signal from
the CNTR
0
pin.
When the CNTR
0
active edge switch bit is “0”, the timer counts
the rising edge of the CNTR
0
pin. When this bit is “1”, the timer
counts the falling edge of the CNTR
0
pin.
Pulse Width Measurement Mode
When the CNTR
0
active edge switch bit is “0”, the timer counts
the signal selected by the timer X count source selection bit while
the CNTR
0
pin is “H”. When this bit is “1”, the timer counts the
signal while the CNTR
0
pin is “L”.
In any mode, the timer count can be stopped by setting the timer
X count stop bit to “1”. Each time the timer overflows, the interrupt
request bit is set.
Fig. 20 Structure of timer X mode register
Fig. 21 Timer count source set register
Timer X mode register
(TXM : address 002B
16
)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR
0
active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X count stop bit
0 : Count start
1 : Count stop
Not used (return “0” when read)
b7 b0
P0
3
/TX
OUT
output valid bit
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR
0
output)
Timer count source set register
(TCSS : address 002E
16
)
Timer X count source selection bits
b1 b0
0 0 : f(X
IN
)/16
0 1 : f(X
IN
)/2
1 0 : f(X
IN
)
1 1 : Not available
b7 b0
Timer Y count source selection bits
b3 b2
0 0 : f(X
IN
)/16
0 1 : f(X
IN
)/2
1 0 : Ring oscillator output (Note)
1 1 : Not available
Timer Z count source selection bits
b5 b4
0 0 : f(X
IN
)/16
0 1 : f(X
IN
)/2
1 0 : Timer Y underflow
1 1 : Not available
Fix this bit to “0”.
Not used (return “0” when read)
Note :
System operates using a ring oscillator as a count source by setting
the ring oscillator to oscillation enabled by bit 3 of CPUM.
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