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參數(shù)資料
| 型號： | M37516RSS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 24/54頁 |
| 文件大小： | 358K |
| 代理商： | M37516RSS |
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M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
GE
Function
In conformity with Philips I
2
C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I
2
C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at
= 4 MHz)
Table 4 Multi-master I
2
C-BUS interface functions
Item
Format
Communication mode
System clock
= f(X
IN
)/2 (high-speed mode)
= f(X
IN
)/8 (middle-speed mode)
MULTI-MASTER I
2
C-BUS INTERFACE
The multi-master I
2
C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I
2
C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchro-
nous functions, is useful for the multi-master serial
communications.
Figure 23 shows a block diagram of the multi-master I
2
C-BUS in-
terface and Table 4 lists the multi-master I
2
C-BUS interface
functions.
This multi-master I
2
C-BUS interface consists of the I
2
C address
register, the I
2
C data shift register, the I
2
C clock control register,
the I
2
C control register, the I
2
C status register, the I
2
C start/stop
condition control register and other control circuits.
When using the multi-master I
2
C-BUS interface, set 1 MHz or
more to
.
Note:
Mitsubishi Electric Corporation assumes no responsibility for in-
fringement of any third-party’s rights or originating in the use of the
connection control function between the I
2
C-BUS interface and the
ports SCL
1
, SCL
2
, SDA
1
and SDA
2
with the bit 6 of I
2
C control regis-
ter (002E
16
).
Fig. 23 Block diagram of multi-master I
2
C-BUS interface
8
: Purchase of MITSUBISHI ELECTRIC CORPORATIONS I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components
an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
SCL clock frequency
I
2
C address register
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
Noise
elimination
circuit
Address comparator
b7
I
2
C data shift register
b0
Data
control
circuit
System clock (f)
Interrupt
generating
circuit
Interrupt request signal
(IICIRQ)
b7
MS
T
TRX BB
PIN
ALAAS AD0 LRB
b0
S1
b7
b0
TISS
SAD
ALS
BC2 BC1
BC0
S1D
Bit counter
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
b7
b0
ACK
ACK
BIT
FAST
CCR4 CCR3 CCR2 CCR1 CCR0
Internal data bus
Clock division
S0
S0D
AL
circuit
ES0
SIS
I
2
C start/stop condition
control register
SIP
SSC4SSC3 SSC2 SSC1 SSC0
I
2
S2
I
2
C status register
S2D
TSEL
I
2
C clock control register
S1D I C control register
2
Serial data
(S
DA
)
Serial
clock
(S
CL
)
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