參數(shù)資料
型號(hào)： M37516RSS
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 42/54頁(yè)
文件大?。?/td> 358K
代理商： M37516RSS
42/54
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
GE
Fig. 51 System clock generating circuit block diagram (Single-chip mode)
MISRG
(MISRG : address 0038
16
)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “01
16
” to Timer 1,
“FF
” to Prescaler 12
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
b7
b0
Fig. 50 Structure of MISRG
Middle-speed mode automatic switch set bit
By setting the middle-speed mode automatic switch set bit to “1”
while operating in the low-speed mode, X
IN
oscillation automati-
cally starts and the mode is automatically switched to the
middle-speed mode when defecting a rising/falling edge of the
SCL or SDA pin. The middle-speed automatic switch wait time set
bit can select the switch timing from the low-speed to the middle-
speed mode; either 4.5 to 5.5 machine cycles or 6.5 to 7.5
machine cycles in the low-speed mode. Select it according to os-
cillation start characteristics of used X
IN
oscillator.
The middle-speed mode automatic switch start bit is used to auto-
matically make to X
IN
oscillation start and switch to the
middle-speed mode by setting this bit to “1” while operating in the
low-speed mode.
WIT instruction
STP instruction
Timing
φ
(internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
S
R
Q
1/2
1/4
X
IN
X
OUT
X
COUT
X
CIN
Interrupt request
Reset
Interrupt disable flag l
1/2
Port X
C
switch bit
“1”
“0”
Low-speed mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits
(Note)
Note 1:
Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b1) to “1”.
2:
When the oscillation stabilizing time set after STP instruction released bit is “0”.
Main clock division ratio
selection bits
(Note 1)
FF
16
01
16
Prescaler 12
Timer 1
Reset or
STP instruction
(Note 2)
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