參數(shù)資料
型號： M37280MK-104SP
廠商： Mitsubishi Electric Corporation
英文描述： Oscillator; Frequency:16MHz; Frequency Tolerance:+/-100ppm; Load Capacitance:50pF; Supply Voltage:5V; Crystal Terminals:Surface Mount (SMD, SMT); Fundamental Mode:Parallel Load; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 22/178頁
文件大?。?/td> 1457K
代理商： M37280MK-104SP
22
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Rev. 1.0
(4) Serial I/O Interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
(5) f(X
IN
)/4096 SPRITE OSD Interrupt
The f (X
IN
)/4096 interrupt occurs regularly with a f(X
IN
)/4096 pe-
riod. Set bit 0 of the PWM mode register 1 to “0.”
The SPRITE OSD interrupt occurs at the completion of SPRITE
display.
Since f(X
IN
)/4096 interrupt and SPRITE OSD interrupt share the
same vector, an interrupt source is selected by bit 5 of the SPRITE
OSD control register (address 0258
16
).
(6) Data Slicer Interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I
2
C-BUS Interface Interrupt
This is an interrupt request related to the multi-master I
2
C-BUS
interface.
(8) A-D Conversion INT3 Interrupt
The A-D conversion interrupt occurs at the completion of A-D
conversion.
The INT3 is an external input,the system detects that the level of
a pin changes from LOW to HIGH or from HIGH to LOW, and
generates an interrupt request. The input active edge can be
selected by bit 6 of the interrupt input polarity register (address
0212
16
) : when this bit is “0,” a change from LOW to HIGH is
detected; when it is “1,” a change from HIGH to LOW is detected.
Note that this bit is cleared to “0” at reset.
Since A-D conversion interrupt and the INT3 interrupt share the
same vector, an interrupt source is selected by bit 7 of the inter-
rupt interval determination control register (address 0212
16
).
(9) Timer 5 6 Interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(10) BRK Instruction Interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Fig. 12.3.1 Interrupt Control
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt
request
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