參數(shù)資料
型號： M37280MK-104SP
廠商： Mitsubishi Electric Corporation
英文描述： Oscillator; Frequency:16MHz; Frequency Tolerance:+/-100ppm; Load Capacitance:50pF; Supply Voltage:5V; Crystal Terminals:Surface Mount (SMD, SMT); Fundamental Mode:Parallel Load; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 12/178頁
文件大?。?/td> 1457K
代理商： M37280MK-104SP
12
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Rev. 1.0
12. FUNCTIONAL DESCRIPTION
12.1. CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
12.1.1 CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo-
cated at address 00FB
16
.
Fig. 12.1.1 CPU Mode Register
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1
B
After reset
R W
0
0, 1
2
3, 4
1
Name
Functions
Processor mode bits
(CM0, CM1)
0 0: Single-chip mode
0 1:
1 0:
Not available
1 1:
0: 0 page
1: 1 page
Fix these bits to “1.”
1
Stack page selection
bit (CM2) (See note)
1
b1 b0
0
0
5
1
6
0
Main Clock (X
IN
–X
OUT
)
stop bit
(CM6)
Internal system clock
selection bit
(CM7)
CPU mode register (CM) [Address 00FB
16
]
R W
R W
R W
R W
R W
X
COUT
drivability
selection bit (CM5)
0: LOW drive
1: HIGH drive
0: Oscillating
1: Stopped
7
0
R W
0: X
IN
–X
OUT
selected
(high-speed mode)
1: X
CIN
–X
COUT
selected
(low-speed mode)
Note:
This bit is set to “1” after the reset release.
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