參數(shù)資料
型號： M37280MK-104SP
廠商： Mitsubishi Electric Corporation
英文描述： Oscillator; Frequency:16MHz; Frequency Tolerance:+/-100ppm; Load Capacitance:50pF; Supply Voltage:5V; Crystal Terminals:Surface Mount (SMD, SMT); Fundamental Mode:Parallel Load; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 16/178頁
文件大?。?/td> 1457K
代理商： M37280MK-104SP
16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Rev. 1.0
Fig. 12.2.4 Memory Map of Special Function Register 1 (SFR2) (2)
F0
16
F1
16
F2
16
F3
16
F4
16
F5
16
F6
16
F7
16
F8
16
F9
16
FA
16
FB
16
FC
16
FD
16
FE
16
FF
16
E0
16
E1
16
E2
16
E3
16
E4
16
E5
16
E6
16
E7
16
E8
16
E9
16
EA
16
EB
16
EC
16
ED
16
EE
16
EF
16
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
A-D conversion register (AD)
A-D control register (ADCON)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
I
2
C
data shift register (S0)
I
2
C
address register (S0D)
Caption data register 1 (CD1)
Caption data register 2 (CD2)
I
2
C
control register (S1D)
I
2
C
clock control register (S2)
CPU mode
register (CM)
Interrupt request
register 1 (IREQ1)
Interrupt request
register 2 (IREQ2)
Interrupt control
register 1 (ICON1)
Interrupt control
register 2 (ICON2)
I
2
C
status register (S1)
I
SFR1 area (addresses E0
16
to FF
16
)
Address
Register
Bit allocation
State immediately after reset
b0 b7
DSC10
0
CDL10
: Fix to this bit to “0”
(do not write to “1”)
:
Bit allocation
State immediately after reset
Function bit
:
No function bit
: Fix to this bit to “1”
(do not write to “0”)
Name
:
: “0” immediately after reset
: Indeterminate immediately
after reset
0
1
: “1” immediately after reset
1
0
Caption data register 3 (CD3)
Caption data register 4 (CD4)
Caption Position register (CPS)
Data slicer test register 2
Data slicer test register 1
Sync signal counter register (HC)
Clock run-in detect register (CRD)
Data clock position register (DPS)
b7
b0
TM20
TM21
TM22
TM23
TM24
TM10
TM11
TM12
TM13
TM14
CM2
TM1R
TM2R
TM3R
TM4R
OSDR
VSCR
ADR
ICK0
IN1R
DSR
SIOR
TM1E
TM2E
TM3E
TM4E
OSDE
VSCE
IN1E
DSE
SIOE
IN2E
TM25
FF
16
07
16
FF
16
07
16
00
16
TM15
TM16
TM17
TM26
TM27
SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
RBW
LRB
AD0
AAS
AL
PIN
BB
10BIT
SAD
MODE
TRX
MST
BC0
BC1
BC2
ESO
ALS
BSEL0
ACK
BIT
BSEL1
CCR0
0
CCR1
0
CCR2
CCR3
1
CCR4
1
ACK
00
16
1
00
16
00
16
3C
16
CKR
IICR
TM56R
ADE
CKE
IICE
TM56E
TM56S
CM7
CM5
CM6
ADIN0
ADIN1
ADIN2
ADVREF
ADSTR
00
16
00
16
00
16
00
16
DSC11
0
CDL11
DSC12
DSC20
DSC23
DSC24
DSC25
CRD3
CRD4
CRD5
CRD6
CRD7
DPS3
DPS4
DPS5
DPS6
DPS7
CPS0
CPS3
CPS4
00
16
00
16
CPS5
CPS1
CPS2
CPS6
CPS7
HC0
HC3
HC4
HC5
HC1
HC2
0
0
0
0
0
0
0
0
0
1
0
0
00
16
CDH10
CDH13
CDH14
CDH15
CDH11
CDH12
CDH16
CDH17
CDL13
CDL14
CDL15
CDL12
CDL16
CDL17
00
16
00
16
00
16
0
00
16
00
16
00
16
00
16
00
16
D1
D2
D3
D4
D5
D6
D7
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CDH20
CDH23
CDH24
CDH25
CDH21
CDH22
CDH26
CDH27
CDL20
CDL23
CDL24
CDL25
CDL21
CDL22
CDL26
CDL27
00
16
09
16
0
0
0
0
1
0
0
Bank control register (BK)
BK0
BK3
BK1
BK2
BK6
BK7
0
0
0
0
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