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Datailed description
Carry
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Rev.3.00
Aug 06, 2004
page 135 of 151
REJ03B0009-0300Z
4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
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V22 = 0: (ADF) = 1
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Transfers the contents of key-on wakeup control register K0 to register A.
Transfers the contents of register A to key-on wakeup control register K0 .
Transfers the contents of key-on wakeup control register K1 to register A.
Transfers the contents of register A to key-on wakeup control register K1.
Transfers the contents of key-on wakeup control register K2 to register A.
Transfers the contents of register A to key-on wakeup control register K2.
Transferts the contents of register A to port output format control register FR0.
Transferts the contents of register A to port output format control register FR1.
Transferts the contents of register A to port output format control register FR2.
Selects the ceramic resonator for main clock f(XIN).
Selects the RC oscillation circuit for main clock f(XIN).
Selects the quartz-crystal oscillation circuit for main clock f(XIN).
Transfers the contents of clock control regiser RG to register A.
Transfers the contents of clock control regiser MR to register A.
Transfers the contents of register A to clock control register MR.
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4) of register AD to register B,
and the low-order 4 bits (AD3–AD0) of register AD to register A.
(Q13: bit 3 of A/D control register Q1)
Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. (V22: bit 2 of interrupt
control register V2)
Transfers the contents of A/D control register Q1 to register A.
Transfers the contents of register A to A/D control register Q1.
Transfers the contents of A/D control register Q2 to register A.
Transfers the contents of register A to A/D control register Q2.
Transfers the contents of A/D control register Q3 to register A.
Transfers the contents of register A to A/D control register Q3.