參數(shù)資料
型號(hào)： M34583MD-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù)： 102/155頁
文件大小： 985K
代理商： M34583MD-XXXFP
Rev.3.00
Aug 06, 2004
page 48 of 151
REJ03B0009-0300Z
4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 37 Setting registers
A/D control register Q2
AIN0 pin function selected
1
(Bit 3)
(Bit 0)
(7) A/D conversion timing chart
Figure 36 shows the A/D conversion timing chart.
Fig. 36 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which
the analog input from P60/AIN0 pin is A/D converted, and the high-
order 4 bits of the converted data are stored in address M(Z, X, Y)
= (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1),
and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM.
The A/D interrupt is not used in this example.
Instruction clock/6 is selected as the A/D converter operation clock.
Select the AIN0 pin function with the bit 0 of the register Q2. Se-
lect the AIN0 pin function and A/D conversion mode with the
register Q1. Also, the instruction clock divided by 6 is selected
with the register Q3. (refer to Figure 37)
Execute the ADST instruction and start A/D conversion.
Examine the state of ADF flag with the SNZAD instruction to de-
termine the end of A/D conversion.
Transfer the low-order 2 bits of converted data to the high-order
2 bits of register A (TALA instruction).
Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
Transfer the high-order 8 bits of converted data to registers A
and B (TABAD instruction).
Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
A/D control register Q1
AIN0 pin selected
A/D conversion mode
000
0
(Bit 3)
(Bit 0)
: Set an arbitrary value.
ADST instruction
A/D conversion
completion flag (ADF)
2 machine cycles + 10/f(ADCK)
DAC operation signal
A/D control register Q3
Frequency divided by 6
Instruction clock
00
0
(Bit 3)
(Bit 0)
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