
Rev.3.00
Aug 06, 2004
page 53 of 151
REJ03B0009-0300Z
4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Program counter (PC) ..........................................................................................................
Address 0 in page 0 is set to program counter.
Interrupt enable flag (INTE) ..................................................................................................
Power down flag (P) .............................................................................................................
External 0 interrupt request flag (EXF0) ..............................................................................
External 1 interrupt request flag (EXF1) ..............................................................................
Interrupt control register V1 ..................................................................................................
Interrupt control register V2 ..................................................................................................
Interrupt control register I1 ...................................................................................................
Interrupt control register I2 ...................................................................................................
Timer 1 interrupt request flag (T1F) .....................................................................................
Timer 2 interrupt request flag (T2F) .....................................................................................
Timer 3 interrupt request flag (T3F) .....................................................................................
Timer 4 interrupt request flag (T4F) .....................................................................................
Watchdog timer flags (WDF1, WDF2) ..................................................................................
Watchdog timer enable flag (WEF) ......................................................................................
Timer control register PA ......................................................................................................
Timer control register W1 .....................................................................................................
Timer control register W2 .....................................................................................................
Timer control register W3 .....................................................................................................
Timer control register W4 .....................................................................................................
Timer control register W5 .....................................................................................................
Timer control register W6 .....................................................................................................
Clock control register MR .....................................................................................................
Clock control register RG .....................................................................................................
8-bit general register SI ........................................................................................................
A/D conversion completion flag (ADF) .................................................................................
A/D control register Q1 .........................................................................................................
A/D control register Q2 .........................................................................................................
A/D control register Q3 .........................................................................................................
Successive comparison register AD ....................................................................................
Comparator register ..............................................................................................................
Key-on wakeup control register K0 ......................................................................................
Key-on wakeup control register K1 ......................................................................................
Key-on wakeup control register K2 ......................................................................................
Pull-up control register PU0 .................................................................................................
Pull-up control register PU1 .................................................................................................
“” represents undefined.
Fig. 43 Internal state at reset 1
(2) Internal state at reset
Figure 43 and 44 show internal state at reset (they are the same af-
ter system is released from reset). The contents of timers, registers,
flags and RAM except shown in Figure are undefined, so set the
initial value to them.
000
00
0
(Interrupt disabled)
0
(Interrupt disabled)
0
(Interrupt disabled)
0
000
0
000
0
1
0
(Prescaler stopped)
0
(Timer 1 stopped)
0
(Timer 2 stopped)
0
(Timer 3 stopped)
0
(Timer 4 stopped)
0
000
(Period measurement circuit stopped)
0
000
1
111
0
(On-chip oscillator operating)
0
000
0
000
0
000
0
000
0
000
0
000
0
000
0
000