Rev.1.02
Nov 26, 2008
REJ03B0224-0102
455A Group
Note 1. If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest
distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
Fig 80. System clock (STCK) operating condition map
Table 32 Recommended operating conditions 2 (Ta = –20
°C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Unit
Min.
Typ.
Max.
f(XIN)
Oscillation frequency
(with a ceramic resonator)
f(STCK) = f(XIN)VDD = 4.0 V to 5.5 V
6
MHz
VDD = 2.7 V to 5.5 V
4.4
VDD = 2 V to 5.5 V
2.2
VDD = 1.8 V to 5.5 V
1.1
f(STCK) = f(XIN)/2
VDD = 2.7 V to 5.5 V
6
VDD = 2 V to 5.5 V
4.4
VDD = 1.8 V to 5.5 V
2.2
f(STCK) = f(XIN)/4, f(XIN)/8
VDD = 2 V to 5.5 V
6
VDD = 1.8 V to 5.5 V
4.4
f(XIN)
Oscillation frequency
(with an external clock input)
f(STCK) = f(XIN)VDD = 4 V to 5.5 V
4.8
MHz
VDD = 2.7 V to 5.5 V
3.2
VDD = 2 V to 5.5 V
1.6
VDD = 1.8 V to 5.5 V
0.8
f(STCK) = f(XIN)/2
VDD = 2.7 V to 5.5 V
4.8
VDD = 2 V to 5.5 V
3.2
VDD = 1.8 V to 5.5 V
1.6
f(STCK) = f(XIN)/4, f(XIN)/8
VDD = 2 V to 5.5 V
4.8
VDD = 1.8 V to 5.5 V
3.2
f(XCIN)
Oscillation frequency
(at quarts-crystal oscillation)
Quartz-crystal oscillator
50
kHz
f(CNTR)
Timer external input frequency CNTR
f(STCK)/6
Hz
tw(CNTR)
Timer external input period
(“H” and “L” pulse width)
CNTR
3/f(STCK)
s
TPON
Power-on reset circuit valid
supply voltage rising time
VDD = 0
→ 1.8V
100
s
1.1
2.2
4.4
6
1.8 2
2.7
4
5.5
Recommended
operating conditions
with a ceramic resonator
f(STCK)
[MHz]
VDD
[V]
0.8
1.6
3.2
4.8
1.8 2
2.7
4
5.5
Recommended
operating conditions
at external clock oscillation
f(STCK)
[MHz]
VDD
[V]
50
1.8
5.5
Recommended
operating conditions
at quartz-crystal oscillation
f(STCK)
[kHz]
VDD
[V]