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Rev.1.02
Nov 26, 2008
REJ03B0224-0102
455A Group
CONTROL REGISTERS
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.
Interrupt control register V1
at reset : 00002
at power down : 00002
TAV1/TV1A
V13
Timer 2 interrupt enable bit
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
V12
Timer 1 interrupt enable bit
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
V11
Not used
0
This bit has no function, but read/write is enabled.
1
V10
External 0 interrupt enable bit
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
Interrupt control register V2
at reset : 00002
at power down : 00002
R/W
TAV2/TV2A
V23
Not used
0
This bit has no function, but read/write is enabled.
1
V22
Not used
0
This bit has no function, but read/write is enabled.
1
V21
Not used
0
This bit has no function, but read/write is enabled.
1
V20
Timer 3 interrupt enable bit
0
Interrupt disabled (SNZT3 instruction is valid)
1
Interrupt enabled (SNZT3 instruction is invalid)
Interrupt control register I1
at reset : 00002
at power down : state retained
R/W
TAI1/TI1A
I13
0
INT pin input disabled
1
INT pin input enabled
I12
0
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
1
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
I11
INT pin edge detection circuit control bit
0
One-sided edge detected
1
Both edges detected
I10
INT pin timer 1 count start synchronous
circuit selection bit
0
Timer 1 count start synchronous circuit not selected
1
Timer 1 count start synchronous circuit selected