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| 型號(hào)： | M34506M4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| 封裝： | 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20 |
| 文件頁(yè)數(shù)： | 17/114頁(yè) |
| 文件大?。?/td> | 836K |
| 代理商： | M34506M4-XXXFP |
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5
5-2
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
5.1 Outline of the Interrupt Controller
The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break
interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external
interrupts (EI).
The maskable interrupts from internal peripheral I/Os are managed by assigning them one of eight priority levels
including an interrupt-disabled state. If two or more interrupt requests with the same priority level occur at the
same time, their priorities are resolved by predetermined hardware priority. The source of an interrupt request
generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for
internal peripheral I/Os.
On the other hand, the system break interrupt (SBI) is recognized when a low-going transition occurs on the SBI#
signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault
condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register
IE bit status. When the CPU has finished servicing an SBI, shut down or reset the system without returning to the
program that was being executed when the interrupt occurred.
Specifications of the Interrupt Controller are outlined below.
Table 5.1.1 Outline of the Interrupt Controller (ICU)
Item
Specification
Interrupt request source
Maskable interrupt requests from internal peripheral I/Os: 32 sources (Note 1)
System break interrupt request: 1 source (entered from SBI# pin)
Priority management
8 priority levels including an interrupt-disabled state
(However, interrupts with the same priority level have their priorities resolved by fixed
hardware priority.)
Note 1: There are actually a total of 179 interrupt request resources when counted individually, which are grouped into 32
interrupt request resources.
5.1 Outline of the Interrupt Controller
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M34506M2-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| M34507E4FP | 4-BIT, OTPROM, MICROCONTROLLER, PDSO24 |
| M34507M2-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
| M34507M4-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
| M34507M2-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M34507E4FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34507M2-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES |
| M34507M4-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34508G4FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34508G4GP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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