
2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group
Under Development
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
4
Table 2. Outline Performance (1/2)
Functional Block
Features
M32R-FPU core
M32R family CPU core, internally configured in 32-bit
Built-in multiplier-accumulator (32
× 16 + 56)
Basic bus cycle: 15.625 ns (CPU clock frequency at 64 MHz, Internal peripheral clock frequency at 16MHz)
: 12.5 ns (CPU clock frequency at 80 MHz, Internal peripheral clock frequency at 20MHz)
Logical address space: 4G bytes, linear
General-purpose register: 32-bit register
× 16,Control register: 32-bit register × 6
Accumulator: 56-bit
External data bus
16-bit data bus
Instruction set
16-bit/32-bit instruction formats
100 discrete instructions in six addressing modes
Internal flash mem-
ory
M32182F8VFP/M32182F8TFP: 1024K bytes
M32182F3VFP/M32182F3TFP: 384K bytes
Rewrite durability: 100 times
Internal RAM
64K bytes
DMAC
10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral I/O and internal
RAM, and between internal RAMs)
Channels can be cascaded and can operate in combination with internal peripheral I/O
Multijunction timer
37 channels of multijunction timers.
TOP : 16-bit output related timer, 11 channels (single-shot, delayed single-shot, and continuous)
TIO : 16-bit input/output related timer, 10 channels (measure clear, measure free-run, noise processing
input, PWM, single-shot, delayed single-shot, continuous output)
TMS : 16-bit input related timer, 8 channels (measure input)
TML : 32-bit input related timer, 8 channels (measure input)
Flexible timer configuration is possible through interconnection of channels using the clock bus or event bus.
A-D converter
10-bit multifunction A-D converters
Input 12 channels
Scan-based conversion can be switched between N (N = 1–12) channels
Capable of interrupt conversion during scan
8-bit/10-bit readout function
Sample & hold function
Disconnection detector assist function
Injection current bypass circuit
Serial I/O
4 channels (The serial I/Os can be set for synchronous serial I/O or UART.
SIO2, SIO3 are UART mode only)
Real-time Debugger
(RTD)
1-channels dedicated clock-synchronized serial
Entire area of internal RAM
Can access the internal RAM for read/rewrite from outside independently of the CPU, and also generate
an exclusive-use interrupt.
Interrupt controller
Controls interrupts from internal peripheral I/Os
(Priority can be set to one of 8 levels including interrupt disabled)
Wait controller
Controls wait when accessing external extended area
(Chip selects for four external extended areas each can have access extended for 0–7 wait cycles plus
WAIT# signal entered from external source) (Note 1)
CAN
Two channels, each having 16-channel message slots
JTAG
Boundary-Scan function, Built-in SDI debugger function in MITSUBISHI
Clock
M32182F8VF P, M32182F3VFP:
CPU clock: maximum 64 MHz (for CPU, internal ROM, and internal RAM access)
Internal peripheral clock (BCLK): maximum 16 MHz (for peripheral module access)
External input clock (XIN): maximum 8.0 MHz, built-in
×8 PLL circuit
M32182F8TF P, M32182F3TFP:
CPU clock: maximum 80 MHz (for CPU, internal ROM, and internal RAM access)
Internal peripheral clock (BCLK): maximum 20 MHz (for peripheral module access)
External input clock (XIN): maximum 10.0 MHz, built-in
×8 PLL circuit