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參數(shù)資料
| 型號： | M32182F3VFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 2/36頁 |
| 文件大?。?/td> | 292K |
| 代理商： | M32182F3VFP |
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group
Under Development
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
10
Outline of the CPU core
The 32182 Group is built around the M32R RISC CPU core,
and has the instruction set common to all of the M32R fam-
ily microcomputers. To achieve high-precision arithmetic
operation, this microcomputer additionally incorporates a
fully IEEE754 compliant, single-precision FPU.
Instructions are processed in five pipelined stages consist-
ing of instruction fetch, decode, execution, memory access,
and write back. Thanks to its “out-of-order-completion”
mechanism, the M32R CPU allows clock cycle to realize
efficient instruction execution control.
The M32R-FPU internally contains sixteen 32-bit general-
purpose registers. The instruction set consists of 100 dis-
crete instructions, which come in either 16-bit or 32-bit in-
struction format. Use of the 16-bit instruction format helps to
reduce the program code size. Also, the availability of 32-bit
instructions facilitates programming and increases the per-
formance at the same clock speed, as compared to archi-
tectures with segmented address spaces.
Multiply-Accumulate instructions comparable to DSP
The M32R-FPU contains a multiplier/accumulator that can
execute 32-bit
× 16-bit in one cycle. Therefore, it executes a
32-bit
× 32-bit integer multiplication instruction in three cy-
cles.
Also, the M32R-FPU supports the following four multiply-
Accumulate instructions (or multiplication instructions) for
DSP function use.
(1) 16 high-order register bits
× 16 high-order register bits
(2) 16 low-order register bits
× 16 low-order register bits
(3) All 32 register bits
× 16 high-order register bits
(4) All 32 register bits
× 16 low-order register bits
Furthermore, the M32R-FPU has instructions for rounding
the value stored in the accumulator to 16 or 32-bit, and in-
structions for shifting the accumulator value to adjust digits
before storing in a register. Because these instructions also
can be executed in one cycle, DSP comparable data proc-
essing capability can be obtained by using them in combi-
nation with high-speed data transfer instructions such as
Load & Address Update or Store & Address Update.
FPU instructions (12 instructions)
The M32R-FPU supports single-precision, floating-point
arithmetic operations fully compliant with IEEE754 standard.
More specifically, it supports all of the following five excep-
tions and four rounding modes. Because the general-
purpose registers are used for floating-point arithmetic, data
transfer overhead is reduced.
Five exceptions (invalid operation, division by zero, over-
flow, underflow, and inexact)
Four rounding modes (round toward nearest, round to-
ward zero, round toward +
∞, round toward -∞)
Also included are the floating-point multiply and add
(FMADD) and floating-point multiply and subtract (FMSUB)
instructions suitable for butterfly operation in FFT.
Extended instructions (5 instructions)
The M32R-FPU has several instructions implemented in it
as extended instructions such as those to set, clear, and
test bits, those to set and clear data in the processor status
register, and those to automatically increment the address
in which to store a halfword.
Address space
The 32182 Group’s logical address is always handled in width
of 32-bit, providing a linear address space of up to 4G bytes.
The 32182’s address space is divided into the following spaces.
User space
A 2G-byte area from H’0000 0000 to H’7FFF FFFF is the
user space. Located in this space are the user ROM area,
external extended area, internal RAM area, and SFR (Spe-
cial Function Register) area (internal peripheral I/O regis-
ters). Of these, the user ROM area and external extended
area are located differently depending on mode settings.
System space
A 2G-byte area from H’8000 0000 to H’FFFF FFFF is the
system area. This space is reserved for use by develop-
ment tools such as an in-circuit emulator and debug monitor,
and cannot be used by the user.
Built-in flash memory and RAM
The M32182F8VFP/M32182F8TFP contains 1024K bytes
flash memory and 64K bytes RAM, the M32182F3VFP/
M32182F3TFP contains 384K bytes flash memory and 64K
bytes RAM.
The internal flash memory can be programmed while being
mounted on the printed circuit board (on-board program-
ming). Use of flash memory allows the same chip as those
used in mass production to be used beginning with the de-
velopment stage. This means that system development can
be proceeded without having to change the printed circuit
boards during the entire course, from prototype to mass
production.
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PDF描述 |
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| M32182F3TFP | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32196F8UFP | 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32192F8TFP | 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PQFP144 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M32182F8TFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F8TFP#U2 | 制造商:Renesas Electronics Corporation 功能描述:MCU 32-bit M32R RISC 1024KB Flash 5V 144-Pin LQFP |
| M32182F8UFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F8VFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182T2-PTC | 功能描述:DEV CONNECTION CNVTR FOR 32182 G RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標準包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關產品:1-Wire? 設備 產品目錄頁面:1429 (CN2011-ZH PDF) |
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